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Tue, 14 Feb 2023 15:47:11 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT005.mail.protection.outlook.com (10.13.172.238) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6086.24 via Frontend Transport; Tue, 14 Feb 2023 15:47:11 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 14 Feb 2023 09:47:10 -0600 From: Mario Limonciello To: , Andreas Noever , Michael Jamet , "Yehezkel Bernat" CC: , Mario Limonciello , , , Subject: [PATCH 1/2] thunderbolt: Read DROM directly from NVM before trying bit banging Date: Tue, 14 Feb 2023 09:46:45 -0600 Message-ID: <20230214154647.874-2-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230214154647.874-1-mario.limonciello@amd.com> References: <20230214154647.874-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT005:EE_|IA1PR12MB8539:EE_ X-MS-Office365-Filtering-Correlation-Id: c719468f-b030-4bd1-1c01-08db0ea2bc99 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Feb 2023 15:47:11.3761 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c719468f-b030-4bd1-1c01-08db0ea2bc99 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT005.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8539 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Some TBT3 devices have a hard time reliably responding to bit banging requests correctly when connected to AMD USB4 hosts running Linux. These problems are not reported in any other CM, and comparing the implementations the Linux CM is the only one that utilizes bit banging to access the DROM. Other CM implementations access the DROM directly from the NVM instead of bit banging. Adjust the flow to try this on TBT3 devices before resorting to bit banging. Cc: stable@vger.kernel.org Signed-off-by: Mario Limonciello --- drivers/thunderbolt/eeprom.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/thunderbolt/eeprom.c b/drivers/thunderbolt/eeprom.c index c90d22f56d4e1..d9d9567bb938b 100644 --- a/drivers/thunderbolt/eeprom.c +++ b/drivers/thunderbolt/eeprom.c @@ -640,6 +640,10 @@ int tb_drom_read(struct tb_switch *sw) return 0; } + /* TBT3 devices have the DROM as part of NVM */ + if (tb_drom_copy_nvm(sw, &size) == 0) + goto parse; + res = tb_drom_read_n(sw, 14, (u8 *) &size, 2); if (res) return res;