| Message ID | 20220701070928.459135-4-herve.codina@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4,1/3] clk: lan966x: Fix the lan966x clock gate register address | expand |
diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi index 3cb02fffe716..c98e7075c2b4 100644 --- a/arch/arm/boot/dts/lan966x.dtsi +++ b/arch/arm/boot/dts/lan966x.dtsi @@ -458,6 +458,17 @@ cpu_ctrl: syscon@e00c0000 { reg = <0xe00c0000 0x350>; }; + udc: usb@e0808000 { + compatible = "microchip,lan9662-udc", + "atmel,sama5d3-udc"; + reg = <0x00200000 0x80000>, + <0xe0808000 0x400>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks GCK_GATE_UDPHS>, <&nic_clk>; + clock-names = "pclk", "hclk"; + status = "disabled"; + }; + can0: can@e081c000 { compatible = "bosch,m_can"; reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
Add UDPHS (the USB High Speed Device Port controller) support. The both lan966x SOCs (LAN9662 and LAN9668) have the same UDPHS IP. This IP is also the same as the one present in the SAMA5D3 SOC. Signed-off-by: Herve Codina <herve.codina@bootlin.com> --- arch/arm/boot/dts/lan966x.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+)