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Thu, 24 Feb 2022 21:51:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT037.mail.protection.outlook.com (10.13.174.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5017.22 via Frontend Transport; Thu, 24 Feb 2022 21:51:26 +0000 Received: from AUS-LX-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Thu, 24 Feb 2022 15:51:24 -0600 From: Mario Limonciello To: Bjorn Helgaas , Andreas Noever , Mika Westerberg , "open list:PCI SUBSYSTEM" , "open list:THUNDERBOLT DRIVER" , "open list:RADEON and AMDGPU DRM DRIVERS" , "open list:DRM DRIVERS" , "open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS" , "open list:X86 PLATFORM DRIVERS" CC: Michael Jamet , Yehezkel Bernat , Lukas Wunner , , Mario Limonciello Subject: [PATCH v5 2/7] PCI: Move check for old Apple Thunderbolt controllers into a quirk Date: Thu, 24 Feb 2022 15:51:11 -0600 Message-ID: <20220224215116.7138-3-mario.limonciello@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220224215116.7138-1-mario.limonciello@amd.com> References: <20220224215116.7138-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 52fb2aea-6dca-4379-bce7-08d9f7dfce9b X-MS-TrafficTypeDiagnostic: BN8PR12MB4594:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Feb 2022 21:51:26.3841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 52fb2aea-6dca-4379-bce7-08d9f7dfce9b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB4594 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org `pci_bridge_d3_possible` currently checks explicitly for a Thunderbolt controller to indicate that D3 is possible. This is used solely for older Apple systems, due to a variety of factors: * Apple used SW connection manager from the beginning, other manufacturers used a FW connection manager (ICM) * Apple supported D3 initially, other manfuacturers didn't introduced this until the `HotplugSupportInD3` _DSD was introduced in ~2015. Apple has stopped creating new machines with Intel Thunderbolt controllers, and all other manufacturers now support D3 via `HotPlugSupportInD3` so this should be a fixed list. Suggested-by: Mika Westerberg Signed-off-by: Mario Limonciello --- drivers/pci/pci.c | 17 +++++++---- drivers/pci/quirks.c | 67 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index 9ecce435fb3f..01557c950c9f 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -1064,7 +1064,18 @@ static inline bool platform_pci_bridge_d3(struct pci_dev *dev) if (pci_use_mid_pm()) return false; - return acpi_pci_bridge_d3(dev); + if (acpi_pci_bridge_d3(dev)) + return true; + + /* + * This is for Apple machines via a quirk + * Non-Apple machines will use the ACPI property with the same name + * from `acpi_pci_bridge_d3` to indciate support. + */ + if (device_property_read_bool(&dev->dev, "HotPlugSupportInD3")) + return true; + + return false; } /** @@ -2954,10 +2965,6 @@ bool pci_bridge_d3_possible(struct pci_dev *bridge) if (pci_bridge_d3_force) return true; - /* Even the oldest 2010 Thunderbolt controller supports D3. */ - if (bridge->is_thunderbolt) - return true; - /* Platform might know better if the bridge supports D3 */ if (platform_pci_bridge_d3(bridge)) return true; diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index ceeca7d8dd90..f74f50ea0695 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -3756,6 +3756,73 @@ DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, quirk_apple_poweroff_thunderbolt); #endif +/* + * The first machines supporting Intel Thunderbolt were released by Apple, and + * supported a software based connection manager including D3 support, as far + * back as 2010. These machines don't have ACPI companions to declare D3 + * support. + * + * Other manufacturers introduced Thunderbolt shortly after but notably did not + * support: + * - Software based connection manager + * - Runtime power management + * Power management was handled via the BIOS when nothing was plugged in. + * Runtime D3 was later introduced in ~2015 and Microsoft declared when the + * `HotPlugSupportInD3` _DSD was present that they would support D3. + * + * This list is expected to be complete and not grow in the future as Apple + * has stopped producing new x86 models with Intel Thunderbolt controllers. + */ +static void quirk_apple_d3_thunderbolt(struct pci_dev *dev) +{ + struct property_entry properties[] = { + PROPERTY_ENTRY_BOOL("HotPlugSupportInD3"), + {}, + }; + + if (!x86_apple_machine) + return; + + if (device_create_managed_software_node(&dev->dev, properties, NULL)) + pci_warn(dev, "could not add HotPlugSupportInD3 property"); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_2C, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_NHI, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_2C_BRIDGE, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_NHI, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_REDWOOD_RIDGE_4C_BRIDGE, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI, + quirk_apple_d3_thunderbolt); +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE, + quirk_apple_d3_thunderbolt); + /* * Following are device-specific reset methods which can be used to * reset a single function if other methods (e.g. FLR, PM D0->D3) are