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Tue, 15 Feb 2022 00:04:16 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; Received: from SATLEXMB04.amd.com (165.204.84.17) by CO1NAM11FT015.mail.protection.outlook.com (10.13.175.130) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.4975.11 via Frontend Transport; Tue, 15 Feb 2022 00:04:16 +0000 Received: from localhost.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.18; Mon, 14 Feb 2022 18:04:14 -0600 From: Mario Limonciello To: Bjorn Helgaas , Mika Westerberg , "open list:PCI SUBSYSTEM" , "open list:THUNDERBOLT DRIVER" , "open list:RADEON and AMDGPU DRM DRIVERS" , "open list:DRM DRIVERS" , "open list:DRM DRIVER FOR NVIDIA GEFORCE/QUADRO GPUS" CC: Andreas Noever , Michael Jamet , Yehezkel Bernat , "Lukas Wunner" , , Hans de Goede , Mario Limonciello Subject: [PATCH v4 04/10] PCI: Detect PCIe root ports for discrete USB4 controllers Date: Mon, 14 Feb 2022 18:01:54 -0600 Message-ID: <20220215000200.242799-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220215000200.242799-1-mario.limonciello@amd.com> References: <20220215000200.242799-1-mario.limonciello@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f15d4654-f760-4442-f086-08d9f016b521 X-MS-TrafficTypeDiagnostic: MN2PR12MB4989:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230001)(4636009)(36840700001)(46966006)(40470700004)(40460700003)(86362001)(70206006)(70586007)(54906003)(8676002)(966005)(110136005)(316002)(4326008)(36756003)(5660300002)(8936002)(7416002)(356005)(81166007)(6666004)(2616005)(83380400001)(2906002)(36860700001)(44832011)(47076005)(82310400004)(508600001)(336012)(1076003)(26005)(16526019)(186003)(426003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2022 00:04:16.6920 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f15d4654-f760-4442-f086-08d9f016b521 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4989 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Discrete USB4 controllers won't have ACPI nodes specifying which root ports they are linked with when the software connection manager creates tunnels. These PCIe root ports should be marked as external so that existing logic will mark tunneled devices as removable. In order to set the external attribute, use the USB4 DVSEC extended capabability set on these root ports to determine if they are located on a discrete USB4 controller. Suggested-by: Mika Westerberg Link: https://usb.org/sites/default/files/USB4%20Specification%2020211116.zip Signed-off-by: Mario Limonciello --- drivers/pci/probe.c | 50 +++++++++++++++++++++++++++++++++++++++++ include/linux/pci_ids.h | 2 ++ 2 files changed, 52 insertions(+) diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 17a969942d37..a07859c8675f 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -25,6 +25,8 @@ #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ #define CARDBUS_RESERVE_BUSNR 3 +#define PCI_DVSEC_ID_USB4 0x23 + static struct resource busn_resource = { .name = "PCI busn", .start = 0, @@ -1600,6 +1602,52 @@ static void set_pcie_untrusted(struct pci_dev *dev) dev->untrusted = true; } +/* + * Use the fields from the USB4 Designated Vendor Specific Extended Capability + * (DVSEC) for Power Management 1.0 to identify PCIe root ports that are for + * XHCI and PCIe tunneling + */ +static void pci_set_usb4_external(struct pci_dev *dev) +{ + int dvsec_val = 0, pos; + u32 hdr; + + /* + * Table 3-1 "USB4 DVSEC Header fields" says vendors can use + * either the Intel or USB IF vendor ID but should look for + * the appropriate DVSEC ID. + */ + pos = pci_find_dvsec_capability(dev, + PCI_VENDOR_ID_INTEL, + PCI_DVSEC_ID_USB4); + if (pos) { + dvsec_val = 0x06; + } else { + pos = pci_find_dvsec_capability(dev, + PCI_VENDOR_ID_USB_IF, + PCI_DVSEC_ID_USB4); + if (pos) + dvsec_val = 0x01; + } + if (!dvsec_val) + return; + + pci_read_config_dword(dev, pos + PCI_DVSEC_HEADER2, &hdr); + if ((hdr & GENMASK(15, 0)) != dvsec_val) + return; + /* + * Look at the port type field for the expected bits for PCIe tunneling + * and XHCI tunneling + * + * 0x0 - Native Host Interface + * 0x1 - PCIe Tunneled Port + * 0x2 - USB Tunneled Port + * 0x3-0x7 - Reserved + */ + if (hdr & GENMASK(17, 16)) + dev->external_facing = true; +} + static void pci_set_removable(struct pci_dev *dev) { struct pci_dev *parent = pci_upstream_bridge(dev); @@ -1870,6 +1918,8 @@ int pci_setup_device(struct pci_dev *dev) /* Early fixups, before probing the BARs */ pci_fixup_device(pci_fixup_early, dev); + pci_set_usb4_external(dev); + pci_set_removable(dev); pci_info(dev, "[%04x:%04x] type %02x class %#08x\n", diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 61b161d914f0..3faee1af9ace 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2567,6 +2567,8 @@ #define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 +#define PCI_VENDOR_ID_USB_IF 0x1ec0 + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 #define PCI_DEVICE_ID_TEHUTI_3010 0x3010