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Fri, 14 Jan 2022 04:43:29 +0000 From: Robert Hancock To: linux-usb@vger.kernel.org Cc: Thinh.Nguyen@synopsys.com, robh+dt@kernel.org, devicetree@vger.kernel.org, michal.simek@xilinx.com, balbi@kernel.org, gregkh@linuxfoundation.org, mounika.grace.akula@xilinx.com, manish.narani@xilinx.com, Robert Hancock Subject: [PATCH v4 4/5] usb: dwc3: add reference clock FLADJ configuration Date: Thu, 13 Jan 2022 22:42:29 -0600 Message-Id: <20220114044230.2677283-5-robert.hancock@calian.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220114044230.2677283-1-robert.hancock@calian.com> References: <20220114044230.2677283-1-robert.hancock@calian.com> X-ClientProxiedBy: MWHPR02CA0016.namprd02.prod.outlook.com (2603:10b6:300:4b::26) To YT2PR01MB6270.CANPRD01.PROD.OUTLOOK.COM (2603:10b6:b01:4d::14) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 395af504-f966-46c0-304b-08d9d71868f2 X-MS-TrafficTypeDiagnostic: YQBPR0101MB6341:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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However, there is another register field, GFLADJ_REFCLK_FLADJ, which reflects the fractional nanosecond portion of the reference clock period. Add a snps,ref-clock-fladj property to allow configuring this as well. On the Xilinx ZynqMP platform, the reference clock appears to always be 20 MHz, giving a clock period of 50 ns. However, the default value of GFLADJ_REFCLK_FLADJ was 1008 rather than 0 as it should have been, which prevented many USB devices from functioning properly. The psu_init code run by the Xilinx first-stage boot loader sets this value to 0, however when the controller is reset by the dwc3-xilinx layer, the incorrect default value is restored. This configuration property allows ensuring that the correct value is always used. Reviewed-by: Thinh Nguyen Signed-off-by: Robert Hancock --- drivers/usb/dwc3/core.c | 35 +++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 5 +++++ 2 files changed, 40 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f4c09951b517..ad224fb8088e 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -359,6 +359,37 @@ static void dwc3_ref_clk_period(struct dwc3 *dwc) } +/** + * dwc3_ref_clk_fladj - Reference clock period adjustment configuration + * @dwc: Pointer to our controller context structure + * + * GFLADJ_REFCLK_FLADJ should be set based on the fractional portion of the + * reference clock period, where the integer portion is set in GUCTL_REFCLKPER. + * Calculated as: ((125000/ref_clk_period_integer)-(125000/ref_clk_period)) * ref_clk_period + * where ref_clk_period_integer is the period specified in GUCTL_REFCLKPER and + * ref_clk_period is the period including fractional value. + * This value can be specified in the device tree if the default value is incorrect. + * Note that 0 is a valid value. + */ +static void dwc3_ref_clk_fladj(struct dwc3 *dwc) +{ + u32 reg; + u32 reg_new; + + if (DWC3_VER_IS_PRIOR(DWC3, 250A)) + return; + + if (!dwc->ref_clk_fladj_set) + return; + + reg = dwc3_readl(dwc->regs, DWC3_GFLADJ); + reg_new = reg & ~DWC3_GFLADJ_REFCLK_FLADJ_MASK; + reg_new |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, dwc->ref_clk_fladj); + if (reg_new != reg) + dwc3_writel(dwc->regs, DWC3_GFLADJ, reg_new); +} + + /** * dwc3_free_one_event_buffer - Frees one event buffer * @dwc: Pointer to our controller context structure @@ -1033,6 +1064,7 @@ static int dwc3_core_init(struct dwc3 *dwc) /* Adjust Reference Clock Period */ dwc3_ref_clk_period(dwc); + dwc3_ref_clk_fladj(dwc); dwc3_set_incr_burst_type(dwc); @@ -1418,6 +1450,9 @@ static void dwc3_get_properties(struct dwc3 *dwc) &dwc->fladj); device_property_read_u32(dev, "snps,ref-clock-period-ns", &dwc->ref_clk_per); + if (!device_property_read_u32(dev, "snps,ref-clock-fladj", + &dwc->ref_clk_fladj)) + dwc->ref_clk_fladj_set = true; dwc->dis_metastability_quirk = device_property_read_bool(dev, "snps,dis_metastability_quirk"); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index e1cc3f7398fb..5011296786de 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -388,6 +388,7 @@ /* Global Frame Length Adjustment Register */ #define DWC3_GFLADJ_30MHZ_SDBND_SEL BIT(7) #define DWC3_GFLADJ_30MHZ_MASK 0x3f +#define DWC3_GFLADJ_REFCLK_FLADJ_MASK 0x3fff00 /* Global User Control Register*/ #define DWC3_GUCTL_REFCLKPER_MASK 0xffc00000 @@ -985,6 +986,8 @@ struct dwc3_scratchpad_array { * @regs_size: address space size * @fladj: frame length adjustment * @ref_clk_per: reference clock period configuration + * @ref_clk_fladj_set: whether ref_clk_fladj value is set/valid + * @ref_clk_fladj: reference clock period fractional adjustment * @irq_gadget: peripheral controller's IRQ number * @otg_irq: IRQ number for OTG IRQs * @current_otg_role: current role of operation while using the OTG block @@ -1166,6 +1169,8 @@ struct dwc3 { u32 fladj; u32 ref_clk_per; + bool ref_clk_fladj_set; + u32 ref_clk_fladj; u32 irq_gadget; u32 otg_irq; u32 current_otg_role;