From patchwork Tue Mar 16 22:13:04 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Badhri Jagan Sridharan X-Patchwork-Id: 403729 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-26.2 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UPPERCASE_50_75,URIBL_BLOCKED,USER_AGENT_GIT,USER_IN_DEF_DKIM_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21BB7C433DB for ; Tue, 16 Mar 2021 22:14:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id EA10164E90 for ; Tue, 16 Mar 2021 22:14:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230486AbhCPWNl (ORCPT ); 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:message-id:mime-version:subject:from:to:cc; bh=vtgRgwp3OG8K6vsJvF4Dtg98thkG7u9zuASSiMamQUE=; b=P3yp0lilJNAn6yLoetuMIyric3GIKwQq7wcjqKz8YAI1wzo3zo/kkx9lzwTe2M1TcJ v7ZE+5N9B93sSHo9dhK8NUuXTiglssHwXVXdh0P9C2ukYNC7Q3ModBrnRa2fT1oBJcCJ 1bAIC3GJXkeYhXfALXemV/Ady5Rx+YX3a7wfKKYT7AsEhdWyKFI0z/ASQpaKY5SNHit5 3BtnsAb5oE9c/XZIKrJVS47I9ECOA9FqH1wxia6S85KNXxCj5hGEfZj1a1SC8cj/9yDS XkPIZMxNwKpMjapqO9FLvEcK3tnOIDKyFMHXGwJiW5kRZqolpWg1QeLISq3hnfc5zaUq kjtA== X-Gm-Message-State: AOAM530l++G/7c9Q2fAYWZ2R+jvb9PMrJsKslAxclqEZCnOo8U0qBPsq q/E/ek4+FM9vrV10mClW1tPh/MAttDo= X-Google-Smtp-Source: ABdhPJxtuQmNVTMcIyTjuNgp/SF3U6Zj7cJYEHydLeEX3QTW1V8z5873ecf9mE3scX2erSDdHnjubwky9u8= X-Received: from badhri.mtv.corp.google.com ([2620:15c:211:201:e53d:77e7:f975:af74]) (user=badhri job=sendgmr) by 2002:a0c:e9c7:: with SMTP id q7mr2129267qvo.7.1615932790400; Tue, 16 Mar 2021 15:13:10 -0700 (PDT) Date: Tue, 16 Mar 2021 15:13:04 -0700 Message-Id: <20210316221304.391206-1-badhri@google.com> Mime-Version: 1.0 X-Mailer: git-send-email 2.31.0.rc2.261.g7f71774620-goog Subject: [PATCH v1] usb: typec: tcpci: Added few missing TCPCI register definitions From: Badhri Jagan Sridharan To: Guenter Roeck , Heikki Krogerus , Greg Kroah-Hartman Cc: linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, Badhri Jagan Sridharan Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org This change adds some of the register bit definitions from the TCPCI spec: https://www.usb.org/sites/default/files/documents/ usb-port_controller_specification_rev2.0_v1.0_0.pdf Signed-off-by: Badhri Jagan Sridharan Reviewed-by: Heikki Krogerus --- drivers/usb/typec/tcpm/tcpci.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/usb/typec/tcpm/tcpci.h b/drivers/usb/typec/tcpm/tcpci.h index 57b6e24e0a0c..2be7a77d400e 100644 --- a/drivers/usb/typec/tcpm/tcpci.h +++ b/drivers/usb/typec/tcpm/tcpci.h @@ -47,7 +47,10 @@ #define TCPC_TCPC_CTRL 0x19 #define TCPC_TCPC_CTRL_ORIENTATION BIT(0) +#define PLUG_ORNT_CC1 0 +#define PLUG_ORNT_CC2 1 #define TCPC_TCPC_CTRL_BIST_TM BIT(1) +#define TCPC_TCPC_CTRL_EN_LK4CONN_ALRT BIT(6) #define TCPC_EXTENDED_STATUS 0x20 #define TCPC_EXTENDED_STATUS_VSAFE0V BIT(0) @@ -74,21 +77,28 @@ #define TCPC_POWER_CTRL_VCONN_ENABLE BIT(0) #define TCPC_POWER_CTRL_BLEED_DISCHARGE BIT(3) #define TCPC_POWER_CTRL_AUTO_DISCHARGE BIT(4) +#define TCPC_DIS_VOLT_ALRM BIT(5) +#define TCPC_POWER_CTRL_VBUS_VOLT_MON BIT(6) #define TCPC_FAST_ROLE_SWAP_EN BIT(7) #define TCPC_CC_STATUS 0x1d #define TCPC_CC_STATUS_TOGGLING BIT(5) #define TCPC_CC_STATUS_TERM BIT(4) +#define TCPC_CC_STATUS_TERM_RP 0 +#define TCPC_CC_STATUS_TERM_RD 1 +#define TCPC_CC_STATE_SRC_OPEN 0 #define TCPC_CC_STATUS_CC2_SHIFT 2 #define TCPC_CC_STATUS_CC2_MASK 0x3 #define TCPC_CC_STATUS_CC1_SHIFT 0 #define TCPC_CC_STATUS_CC1_MASK 0x3 #define TCPC_POWER_STATUS 0x1e +#define TCPC_POWER_STATUS_DBG_ACC_CON BIT(7) #define TCPC_POWER_STATUS_UNINIT BIT(6) #define TCPC_POWER_STATUS_SOURCING_VBUS BIT(4) #define TCPC_POWER_STATUS_VBUS_DET BIT(3) #define TCPC_POWER_STATUS_VBUS_PRES BIT(2) +#define TCPC_POWER_STATUS_SINKING_VBUS BIT(0) #define TCPC_FAULT_STATUS 0x1f @@ -121,6 +131,10 @@ #define TCPC_RX_DETECT 0x2f #define TCPC_RX_DETECT_HARD_RESET BIT(5) #define TCPC_RX_DETECT_SOP BIT(0) +#define TCPC_RX_DETECT_SOP1 BIT(1) +#define TCPC_RX_DETECT_SOP2 BIT(2) +#define TCPC_RX_DETECT_DBG1 BIT(3) +#define TCPC_RX_DETECT_DBG2 BIT(4) #define TCPC_RX_BYTE_CNT 0x30 #define TCPC_RX_BUF_FRAME_TYPE 0x31 @@ -139,6 +153,8 @@ #define TCPC_TX_DATA 0x54 /* through 0x6f */ #define TCPC_VBUS_VOLTAGE 0x70 +#define TCPC_VBUS_VOLTAGE_MASK 0x3ff +#define TCPC_VBUS_VOLTAGE_LSB_MV 25 #define TCPC_VBUS_SINK_DISCONNECT_THRESH 0x72 #define TCPC_VBUS_SINK_DISCONNECT_THRESH_LSB_MV 25 #define TCPC_VBUS_SINK_DISCONNECT_THRESH_MAX 0x3ff