From patchwork Wed Feb 3 06:31:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 375767 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.0 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, MIME_BASE64_TEXT, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E93CC433E0 for ; Wed, 3 Feb 2021 06:33:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C677064F5D for ; Wed, 3 Feb 2021 06:33:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231186AbhBCGdg (ORCPT ); Wed, 3 Feb 2021 01:33:36 -0500 Received: from Mailgw01.mediatek.com ([1.203.163.78]:51442 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S230072AbhBCGdg (ORCPT ); Wed, 3 Feb 2021 01:33:36 -0500 X-UUID: ea045c50623a494f93a4516e2cc661e0-20210203 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=kvt11SlkOZybA/MDMjfWqmErggnnd9YVI0O6nOjXt5U=; b=a5HQTqRNf3Da2x943rGjd3uhtnG7erUqHDdhYkyVHYCKriNjgu8qpkAhCMmJi9QOsQZxMCSTtcqwoZVt1oPsHrTMl1exOPS2Yj0fvMxyXLAE/nmrTIq5x+deu05vFxVhOH6qa/1GMZsXeyAqwEJ2PNW7cwm3SslkNRWbvw4XGYc=; X-UUID: ea045c50623a494f93a4516e2cc661e0-20210203 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1385229869; Wed, 03 Feb 2021 14:32:48 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 3 Feb 2021 14:32:45 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Wed, 3 Feb 2021 14:32:45 +0800 From: Chunfeng Yun To: Rob Herring , Matthias Brugger , Mathias Nyman CC: Greg Kroah-Hartman , , , , , , Ikjoon Jang , Nicolas Boichat , Chunfeng Yun Subject: [RFC PATCH 1/3] dt-bindings: usb: mtk-xhci: add compatible for mt8195 Date: Wed, 3 Feb 2021 14:31:57 +0800 Message-ID: <20210203063159.11021-1-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 2.18.0 MIME-Version: 1.0 X-TM-SNTS-SMTP: DB33ADAD09D7543E95313A04B7A5561973C6E8CA455E17167FA0A7B3AE61E4762000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org There are 4 USB controllers on MT8195, the controllers (IP1~IP3, exclude IP0) have a wrong default SOF/ITP interval which is calculated from the frame counter clock 24Mhz by default, but in fact, the frame counter clock is 48Mhz, so we should set the accurate interval according to 48Mhz. Here add a new compatible for MT8195, it's also supported in driver. But the first controller (IP0) has no such issue, we prefer to use generic compatible, e.g. mt8192's compatible. Signed-off-by: Chunfeng Yun --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 + 1 file changed, 1 insertion(+) -- 2.18.0 diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt index 42d8814f903a..02cba4212f7d 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt @@ -16,6 +16,7 @@ Required properties: "mediatek,mtk-xhci" compatible string, you need SoC specific ones in addition, one of: - "mediatek,mt8173-xhci" + - "mediatek,mt8195-xhci" - reg : specifies physical base address and size of the registers - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control - interrupts : interrupt used by the controller