From patchwork Wed Sep 9 08:10:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: JC Kuo X-Patchwork-Id: 297688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37E0FC2D0A8 for ; Wed, 9 Sep 2020 08:14:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E3E4121D7B for ; Wed, 9 Sep 2020 08:14:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="IaC/r3lT" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725917AbgIIILA (ORCPT ); Wed, 9 Sep 2020 04:11:00 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:14026 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730077AbgIIIK4 (ORCPT ); Wed, 9 Sep 2020 04:10:56 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 09 Sep 2020 01:08:40 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 09 Sep 2020 01:10:55 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 09 Sep 2020 01:10:55 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 9 Sep 2020 08:10:50 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 9 Sep 2020 08:10:49 +0000 Received: from jckuo-lt.nvidia.com (Not Verified[10.19.100.126]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 09 Sep 2020 01:10:49 -0700 From: JC Kuo To: , , , , CC: , , , , , JC Kuo Subject: [PATCH v3 02/15] clk: tegra: Don't enable PLLE HW sequencer at init Date: Wed, 9 Sep 2020 16:10:28 +0800 Message-ID: <20200909081041.3190157-3-jckuo@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200909081041.3190157-1-jckuo@nvidia.com> References: <20200909081041.3190157-1-jckuo@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1599638920; bh=YuKOxLECL/634zGae4BZvw33u7t46u6t6eEAszbgUK8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:X-NVConfidentiality: Content-Transfer-Encoding:Content-Type; b=IaC/r3lTco2lCMtfpNnutLt226rzvq0Ejk1YggCfyj/KIk0x2kC17zKhXyjlxxX+C yfBdqRaay7wtd4Q8Xb2XTCLggJG4M95ySVlfmdXo8LLtxX/oABLcuRj4By4tkEOnev dB3G5xYaCTSBibdQ/INajZMQ+vUN/7CMwrv8tHWMP9Bwbx/qX7Nw/5Pi2VneYuWZ1V AuHD9ER5yAJEh+lt2kh33HuzGhU1P73sKcCEGxjfMzQtrIptzQzWVqMiKVIQHygYia qv1CeKmtvqCcFg+idRmHL0qeF1IvDzWZn4vPkFc+cXyoMxubM6jC13T9fdm5Mdq5LH vXcoSxpgeXbZg== Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org PLLE hardware power sequencer references PEX/SATA UPHY PLL hardware power sequencers' output to enable/disable PLLE. PLLE hardware power sequencer has to be enabled only after PEX/SATA UPHY PLL's sequencers are enabled. Signed-off-by: JC Kuo --- v3: no change drivers/clk/tegra/clk-pll.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index c5cc0a2dac6f..0193cebe8c5a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -2515,18 +2515,6 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) pll_writel(val, PLLE_SS_CTRL, pll); udelay(1); - val = pll_readl_misc(pll); - val &= ~PLLE_MISC_IDDQ_SW_CTRL; - pll_writel_misc(val, pll); - - val = pll_readl(pll->params->aux_reg, pll); - val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE); - val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL); - pll_writel(val, pll->params->aux_reg, pll); - udelay(1); - val |= PLLE_AUX_SEQ_ENABLE; - pll_writel(val, pll->params->aux_reg, pll); - out: if (pll->lock) spin_unlock_irqrestore(pll->lock, flags);