From patchwork Thu Apr 6 10:17:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Felipe Balbi X-Patchwork-Id: 96918 Delivered-To: patch@linaro.org Received: by 10.140.89.233 with SMTP id v96csp659736qgd; Thu, 6 Apr 2017 03:18:18 -0700 (PDT) X-Received: by 10.98.79.90 with SMTP id d87mr34667767pfb.126.1491473897942; Thu, 06 Apr 2017 03:18:17 -0700 (PDT) Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id n59si1424084plb.21.2017.04.06.03.18.17; Thu, 06 Apr 2017 03:18:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-usb-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@intel.com; spf=pass (google.com: best guess record for domain of linux-usb-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-usb-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754405AbdDFKSO (ORCPT + 4 others); Thu, 6 Apr 2017 06:18:14 -0400 Received: from mga14.intel.com ([192.55.52.115]:57956 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754540AbdDFKSJ (ORCPT ); Thu, 6 Apr 2017 06:18:09 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1491473889; x=1523009889; h=from:to:cc:subject:date:message-id; bh=pQEmn4G7BNYQPqL1KWlnz5XVFeU4I+2vp8n377JgMHQ=; b=lJ4OTQMn74kQ0Zx6zG81dzmkbXx56sHGqiYWpJ2QvjXxgCrJxjIqYA/X SYFeAKbBs8pgGfEzXT4hpH0zpYVwfA==; Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Apr 2017 03:18:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,159,1488873600"; d="scan'208";a="1151899779" Received: from pipin.fi.intel.com (HELO localhost) ([10.237.68.37]) by fmsmga002.fm.intel.com with ESMTP; 06 Apr 2017 03:18:07 -0700 From: Felipe Balbi To: Linux USB Cc: Roger Quadros , Felipe Balbi Subject: [PATCH] usb: dwc3: make macros safe to expression arguments Date: Thu, 6 Apr 2017 13:17:54 +0300 Message-Id: <20170406101754.14585-1-felipe.balbi@linux.intel.com> X-Mailer: git-send-email 2.11.0.295.gd7dffce1ce Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Roger Quadros We must make sure that our macros are safe against expressions passed as arguments. We have see one problem where GTXFIFOSIZ(n) was failling when passed the expression (epnum >> 1) as argument. The problem was caused by operator precedence between >> and *. To make sure macros are safe, we just wrap argument with () when using it. Signed-off-by: Roger Quadros Signed-off-by: Felipe Balbi --- As discussed over IRC, Roger figured out what was the problem with "Bryan's patch". It turns out that GTXFIFOSIZ() macro wasn't safe against expression arguments. Roger provided a patch, which I'm now sending to linux-usb in his regard. drivers/usb/dwc3/core.h | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) -- 2.11.0.295.gd7dffce1ce -- To unsubscribe from this list: send the line "unsubscribe linux-usb" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 459ecf3afa48..8a0fbcd99638 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -117,20 +117,20 @@ #define DWC3_VER_NUMBER 0xc1a0 #define DWC3_VER_TYPE 0xc1a4 -#define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04)) -#define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04)) +#define DWC3_GUSB2PHYCFG(n) (0xc200 + ((n) * 0x04)) +#define DWC3_GUSB2I2CCTL(n) (0xc240 + ((n) * 0x04)) -#define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04)) +#define DWC3_GUSB2PHYACC(n) (0xc280 + ((n) * 0x04)) -#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04)) +#define DWC3_GUSB3PIPECTL(n) (0xc2c0 + ((n) * 0x04)) -#define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04)) -#define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04)) +#define DWC3_GTXFIFOSIZ(n) (0xc300 + ((n) * 0x04)) +#define DWC3_GRXFIFOSIZ(n) (0xc380 + ((n) * 0x04)) -#define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10)) -#define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10)) -#define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) -#define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10)) +#define DWC3_GEVNTADRLO(n) (0xc400 + ((n) * 0x10)) +#define DWC3_GEVNTADRHI(n) (0xc404 + ((n) * 0x10)) +#define DWC3_GEVNTSIZ(n) (0xc408 + ((n) * 0x10)) +#define DWC3_GEVNTCOUNT(n) (0xc40c + ((n) * 0x10)) #define DWC3_GHWPARAMS8 0xc600 #define DWC3_GFLADJ 0xc630 @@ -144,13 +144,13 @@ #define DWC3_DGCMD 0xc714 #define DWC3_DALEPENA 0xc720 -#define DWC3_DEP_BASE(n) (0xc800 + (n * 0x10)) +#define DWC3_DEP_BASE(n) (0xc800 + ((n) * 0x10)) #define DWC3_DEPCMDPAR2 0x00 #define DWC3_DEPCMDPAR1 0x04 #define DWC3_DEPCMDPAR0 0x08 #define DWC3_DEPCMD 0x0c -#define DWC3_DEV_IMOD(n) (0xca00 + (n * 0x4)) +#define DWC3_DEV_IMOD(n) (0xca00 + ((n) * 0x4)) /* OTG Registers */ #define DWC3_OCFG 0xcc00 @@ -460,7 +460,7 @@ #define DWC3_DEPCMD_CMD(x) ((x) & 0xf) /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */ -#define DWC3_DALEPENA_EP(n) BIT(n) +#define DWC3_DALEPENA_EP(n) BIT((n)) #define DWC3_DEPCMD_TYPE_CONTROL 0 #define DWC3_DEPCMD_TYPE_ISOC 1