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Tue, 7 Jun 2022 02:33:39 +0000 From: Li Jun To: gregkh@linuxfoundation.org, balbi@kernel.org Cc: linux-usb@vger.kernel.org, Thinh.Nguyen@synopsys.com, jindong.yue@nxp.com Subject: [PATCH v3] usb: dwc3: add power down scale setting Date: Tue, 7 Jun 2022 10:20:04 +0800 Message-Id: <1654568404-3461-1-git-send-email-jun.li@nxp.com> X-Mailer: git-send-email 2.7.4 X-ClientProxiedBy: SG3P274CA0022.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:be::34) To PA4PR04MB9640.eurprd04.prod.outlook.com (2603:10a6:102:261::21) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 50f76f09-e59d-43e0-8430-08da482e2125 X-MS-TrafficTypeDiagnostic: VI1PR0402MB2893:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2/5khHb4vSMn6cpeDWy0J8Q6pcxmJ0I+Ksg6Bb7+TQ51xWyCGcOiB+Jdn4NECphk7uPf2SYmjyz2OFXm+851agOQMBFuXgLCP+zyEYoRwySPA29o8MsQL+OfdFwDFHdKYccg7ojV7U8yDlbXE/PXwlShnTC2Q/uneLKHg5VLVDywmszs0w0FN+Ze2LfNJBhFLAiHJRJMpbMvSjj5kPcs5KgWBwu1Gw+BoTgNQ/ELeTsDxmxcO83Yl/eNAvK/Cek9JT7poRo9WRZKtVdnMNCHDpWEfLAs/LopbGE1VzsgjmUviib7PVPDbrdy+jypwIx20n2HtCRoe8JPSso8P7oHU0znsvF84t9xOYC2hEP1YbL+EvQfZud67WWp+6q8d7q8/6kCyoY5teguSJD2330KcKpavGleJjmcnF2YWHpXHcRYpI4dlBptua9zEFdjFk96kJd2NZ3yRnFZ5PV6B75YrDyrOXyu9mKC42NRcL8FKgihNm1gVB7dd0vUZwSxevjkQ7A+Q1ex0/cE4YyrSb/K9RNAU+VB6bqfC9L5iJFXeMmwkCZQ2ilzOnSlJJUKoQ+AJqznno8lrghUoy+uiQ/OQV1C6no/Lv6JWACCuS6xY+Y0nVSOtcrhWOe3tLsd5kRqv6UtktqF09D1KK8loHo0hX8l4AjqgGcZjaO0z2tCLJc01GlKwJVZcpPOavXwhnKdY9lt2BTJ06NfGGEo7u8n2A== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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The Power Down Scale field specifies how many suspend_clk periods fit into a 16 kHz clock period. When performing the division, round up the remainder. For example, when using an 8-bit/16-bit/32-bit PHY and 25-MHz Suspend clock, Power Down Scale = 25000 kHz/16 kHz = 13'd1563 (rounder up) So use the suspend clock rate to calculate it. Reviewed-by: Thinh Nguyen Signed-off-by: Li Jun --- Changes for v3: - Refine the code comments for why we need do this as Thinh suggested. - Add Thinh's R-b tag. Changes for v2: - Add PwrDnScale field update condition: less than the calculated value or more than 3x the calculated value. - Correct 16k from 16384 to 16000. - Delare variables in separate lines. drivers/usb/dwc3/core.c | 34 ++++++++++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 1 + 2 files changed, 35 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index e027c0420dc3..b4c47002828c 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1029,6 +1029,37 @@ static void dwc3_set_incr_burst_type(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg); } +static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc) +{ + u32 scale; + u32 reg; + + if (!dwc->susp_clk) + return; + + /* + * The power down scale field specifies how many suspend_clk + * periods fit into a 16KHz clock period. When performing + * the division, round up the remainder. + * + * The power down scale value is calculated using the fastest + * frequency of the suspend_clk. If it isn't fixed (but within + * the accuracy requirement), the driver may not know the max + * rate of the suspend_clk, so only update the power down scale + * if the default is less than the calculated value from + * clk_get_rate() or if the default is questionably high + * (3x or more) to be within the requirement. + */ + scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000); + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) || + (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) { + reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK); + reg |= DWC3_GCTL_PWRDNSCALE(scale); + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + } +} + /** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure @@ -1105,6 +1136,9 @@ static int dwc3_core_init(struct dwc3 *dwc) if (ret) goto err1; + /* Set power down scale of suspend_clk */ + dwc3_set_power_down_clk_scale(dwc); + /* Adjust Frame Length */ dwc3_frame_length_adjustment(dwc); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 81c486b3941c..722808d8c0af 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -231,6 +231,7 @@ /* Global Configuration Register */ #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) +#define DWC3_GCTL_PWRDNSCALE_MASK GENMASK(31, 19) #define DWC3_GCTL_U2RSTECN BIT(16) #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6) #define DWC3_GCTL_CLK_BUS (0)