From patchwork Tue Feb 15 19:19:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandeep Maheswaram X-Patchwork-Id: 542988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 169CAC433FE for ; Tue, 15 Feb 2022 19:20:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243699AbiBOTUi (ORCPT ); Tue, 15 Feb 2022 14:20:38 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:54810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243649AbiBOTUZ (ORCPT ); Tue, 15 Feb 2022 14:20:25 -0500 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1E12811596B; Tue, 15 Feb 2022 11:19:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644952792; x=1676488792; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version; bh=+c/sAVWbL+FsYmpW5HTm4iUSXm3Ddt3ihcr9mqI4b2I=; b=fnPR4MITCOhMyOaujZ3EGk7wJQqit/7QW84jqPttvsV+R8XO9acRWROD bqcQdpFmcfXLo8rSc8OSxsV4HAxOCb5r3gtRXsMgj7T1+4bJvBKj0mhwm 9naGo38xxdZKMOmiD1yjdRXrJTjk1ESjCKhMRUClt8hYZtZzEyT4Ol3gf U=; Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-01.qualcomm.com with ESMTP; 15 Feb 2022 11:19:51 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg02-sd.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Feb 2022 11:19:50 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.15; Tue, 15 Feb 2022 11:19:50 -0800 Received: from c-sanm-linux.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Tue, 15 Feb 2022 11:19:44 -0800 From: Sandeep Maheswaram To: Rob Herring , Krzysztof Kozlowski , Andy Gross , "Bjorn Andersson" , Kishon Vijay Abraham I , Vinod Koul , Greg Kroah-Hartman , Wesley Cheng , "Stephen Boyd" , Doug Anderson , "Matthias Kaehlcke" CC: , , , , , , , Sandeep Maheswaram Subject: [PATCH 2/3] phy: qcom-snps: Add support for overriding phy tuning parameters Date: Wed, 16 Feb 2022 00:49:14 +0530 Message-ID: <1644952755-15527-3-git-send-email-quic_c_sanm@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1644952755-15527-1-git-send-email-quic_c_sanm@quicinc.com> References: <1644952755-15527-1-git-send-email-quic_c_sanm@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Added support for overriding x0,x1,x2,x3 params for SNPS PHY. Signed-off-by: Sandeep Maheswaram --- drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c | 45 +++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c index 7e61202..3cf90fa 100644 --- a/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c +++ b/drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c @@ -51,6 +51,12 @@ #define USB2_SUSPEND_N BIT(2) #define USB2_SUSPEND_N_SEL BIT(3) +#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0 (0x6c) +#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1 (0x70) +#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2 (0x74) +#define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78) +#define PARAM_OVRD_MASK 0xFF + #define USB2_PHY_USB_PHY_CFG0 (0x94) #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) @@ -90,6 +96,11 @@ struct qcom_snps_hsphy { bool phy_initialized; enum phy_mode mode; + + u8 override_x0; + u8 override_x1; + u8 override_x2; + u8 override_x3; }; static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, @@ -222,6 +233,19 @@ static int qcom_snps_hsphy_init(struct phy *phy) qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, VBUSVLDEXT0, VBUSVLDEXT0); + if (hsphy->override_x0) + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0, + PARAM_OVRD_MASK, hsphy->override_x0); + if (hsphy->override_x1) + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, + PARAM_OVRD_MASK, hsphy->override_x1); + if (hsphy->override_x2) + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2, + PARAM_OVRD_MASK, hsphy->override_x2); + if (hsphy->override_x3) + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3, + PARAM_OVRD_MASK, hsphy->override_x3); + qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, VREGBYPASS, VREGBYPASS); @@ -294,6 +318,7 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev) struct phy *generic_phy; int ret, i; int num; + u32 value; hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL); if (!hsphy) @@ -329,6 +354,26 @@ static int qcom_snps_hsphy_probe(struct platform_device *pdev) return ret; } + if (!of_property_read_u32(dev->of_node, "qcom,override_x0", + &value)) { + hsphy->override_x0 = (u8)value; + } + + if (!of_property_read_u32(dev->of_node, "qcom,override_x1", + &value)) { + hsphy->override_x1 = (u8)value; + } + + if (!of_property_read_u32(dev->of_node, "qcom,override_x2", + &value)) { + hsphy->override_x2 = (u8)value; + } + + if (!of_property_read_u32(dev->of_node, "qcom,override_x3", + &value)) { + hsphy->override_x3 = (u8)value; + } + pm_runtime_set_active(dev); pm_runtime_enable(dev); /*