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CAT:NONE; SFS:(4636009)(346002)(136003)(39860400002)(396003)(376002)(46966006)(36840700001)(86362001)(47076005)(336012)(70206006)(8936002)(36860700001)(8676002)(16526019)(186003)(70586007)(26005)(6666004)(83380400001)(36756003)(82310400003)(2906002)(316002)(426003)(2616005)(82740400003)(4326008)(356005)(5660300002)(81166007)(54906003)(478600001)(110136005)(7696005)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Aug 2021 12:58:45.9417 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2403fd50-9f82-415e-73e7-08d955b54397 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT038.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1398 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanjay R Mehta when the "Disable ISR Auto-Clear" bit is set, the Tx/Rx ring interrupt status is not cleared. Hence handling it by setting the "Interrupt status clear" register to clear the corresponding Tx/Rx ring interrupt. Signed-off-by: Basavaraj Natikar Signed-off-by: Sanjay R Mehta --- drivers/thunderbolt/nhi.c | 26 +++++++++++++++++++++++++- include/linux/thunderbolt.h | 1 + 2 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/thunderbolt/nhi.c b/drivers/thunderbolt/nhi.c index d7d9c4b..63bbabf 100644 --- a/drivers/thunderbolt/nhi.c +++ b/drivers/thunderbolt/nhi.c @@ -74,7 +74,11 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active) if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { misc |= REG_DMA_MISC_INT_AUTO_CLEAR; iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); - } + misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); + if (misc & REG_DMA_MISC_INT_AUTO_CLEAR) + ring->nhi->is_intr_autoclr = true; + } else + ring->nhi->is_intr_autoclr = true; ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; @@ -377,11 +381,31 @@ void tb_ring_poll_complete(struct tb_ring *ring) } EXPORT_SYMBOL_GPL(tb_ring_poll_complete); +static void check_and_clear_intr_status(struct tb_ring *ring, int int_pos) +{ + u32 value; + + if (!ring->nhi->is_intr_autoclr) { + value = ioread32(ring->nhi->iobase + + REG_RING_NOTIFY_BASE + + 4 * (int_pos / 32)); + iowrite32(value, ring->nhi->iobase + + (REG_RING_NOTIFY_BASE + 8) + + 4 * (int_pos / 32)); + } +} + static irqreturn_t ring_msix(int irq, void *data) { struct tb_ring *ring = data; spin_lock(&ring->nhi->lock); + + if (ring->is_tx) + check_and_clear_intr_status(ring, 0); + else + check_and_clear_intr_status(ring, ring->nhi->hop_count); + spin_lock(&ring->lock); __ring_interrupt(ring); spin_unlock(&ring->lock); diff --git a/include/linux/thunderbolt.h b/include/linux/thunderbolt.h index e7c96c3..bbe7c7e 100644 --- a/include/linux/thunderbolt.h +++ b/include/linux/thunderbolt.h @@ -478,6 +478,7 @@ struct tb_nhi { struct tb_ring **rx_rings; struct ida msix_ida; bool going_away; + bool is_intr_autoclr; struct work_struct interrupt_work; u32 hop_count; };