From patchwork Tue Dec 22 09:34:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 346872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, UNPARSEABLE_RELAY, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0B947C433E0 for ; Tue, 22 Dec 2020 09:36:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDFE523103 for ; Tue, 22 Dec 2020 09:36:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725913AbgLVJfp (ORCPT ); Tue, 22 Dec 2020 04:35:45 -0500 Received: from mailgw02.mediatek.com ([1.203.163.81]:3991 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725895AbgLVJfo (ORCPT ); Tue, 22 Dec 2020 04:35:44 -0500 X-UUID: 1f47d6a946494a5996f43e801bdcac1f-20201222 X-UUID: 1f47d6a946494a5996f43e801bdcac1f-20201222 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 253076222; Tue, 22 Dec 2020 17:34:59 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 22 Dec 2020 17:34:57 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 22 Dec 2020 17:34:55 +0800 From: Chunfeng Yun To: Ikjoon Jang CC: Chunfeng Yun , Tianping Fang , Zhanyong Wang , , , , Zhanyong Wang Subject: [RFC PATCH v3 5/5] arm64: dts: mt8192: add SSUSB related nodes Date: Tue, 22 Dec 2020 17:34:42 +0800 Message-ID: <1608629682-8535-5-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1608629682-8535-1-git-send-email-chunfeng.yun@mediatek.com> References: <1608629682-8535-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 13DABBDEFD78ED4A7DB3C280B058F72B960972A49665467DDC424A771ACA78A32000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Zhanyong Wang Add SSUSB related nodes for mt8192 Signed-off-by: Zhanyong Wang Signed-off-by: Chunfeng Yun --- v3: rename node as 'usb' instead of xhci v2: include phy.h file Depends on: https://patchwork.kernel.org/patch/11713559/ [v4,1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 49 ++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 69d45c7b31f1..82d9f6eee404 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -9,6 +9,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -416,6 +417,54 @@ status = "disabled"; }; + xhci: usb@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 211 IRQ_TYPE_LEVEL_LOW>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg CLK_INFRA_SSUSB>, + <&infracfg CLK_INFRA_SSUSB_XHCI>, + <&apmixedsys CLK_APMIXED_USBPLL>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + mediatek,syscon-wakeup = <&pericfg 0x420 3>; + #address-cells = <2>; + #size-cells = <2>; + }; + + u3phy0: usb-phy@11e40000 { + compatible = "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port0: usb-phy@11e40000 { + reg = <0 0x11e40000 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11e40700 { + reg = <0 0x11e40700 0 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + audsys: syscon@11210000 { compatible = "mediatek,mt8192-audsys", "syscon"; reg = <0 0x11210000 0 0x1000>;