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dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="A1hKaZmt" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728244AbgICDbt (ORCPT ); Wed, 2 Sep 2020 23:31:49 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:5703 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726821AbgICDb0 (ORCPT ); Wed, 2 Sep 2020 23:31:26 -0400 X-UUID: baf6f1abbe9c439f8b49170cf5ea3b28-20200903 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=G+l2nCRr0+/8nka2nngFFVIR8XrakSr3N56sAqsrVVs=; b=A1hKaZmtmRmjMY2wjjyNJ8HgS7IRd0EGI1MN2d+SFo3qiS9wMOgUpFRV/qrwBpm/1wRJywDK3A1N/yJVzqvakaRfFtSZHkvGfY34/2x0CtKK7lMnRBnsRXq4FGeNsTMQV1MRb5/q2j/+GRrImFj76KnqmQSqhaW3niL4r2uQ6hk=; X-UUID: baf6f1abbe9c439f8b49170cf5ea3b28-20200903 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1915563420; Thu, 03 Sep 2020 11:31:20 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 3 Sep 2020 11:31:17 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 3 Sep 2020 11:31:17 +0800 From: Chunfeng Yun To: Zhanyong Wang CC: , , , , Chunfeng Yun Subject: [RFC PATCH 4/4] arm64: dts: mt8192: add SSUSB related nodes Date: Thu, 3 Sep 2020 11:28:59 +0800 Message-ID: <1599103739-7873-4-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1599103739-7873-1-git-send-email-chunfeng.yun@mediatek.com> References: <1599103739-7873-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 555095332610F26608A183E1336A0372661BB41058C02440A34D47EEA584F1BA2000:8 X-MTK: N Sender: linux-usb-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Zhanyong Wang Add SSUSB related nodes for mt8192 Signed-off-by: Zhanyong Wang Signed-off-by: Chunfeng Yun --- Depends on: https://patchwork.kernel.org/patch/11713559/ [v4,1/3] arm64: dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 1.9.1 diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 8871c2f..755f152 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -434,6 +434,54 @@ status = "disabled"; }; + xhci: xhci@11200000 { + compatible = "mediatek,mt8192-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts-extended = <&gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>, + <&pio 211 IRQ_TYPE_LEVEL_LOW>; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>; + assigned-clocks = <&topckgen CLK_TOP_USB_TOP_SEL>, + <&topckgen CLK_TOP_SSUSB_XHCI_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, + <&topckgen CLK_TOP_UNIVPLL_D5_D4>; + clocks = <&infracfg CLK_INFRA_SSUSB>, + <&infracfg CLK_INFRA_SSUSB_XHCI>, + <&apmixedsys CLK_APMIXED_USBPLL>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + mediatek,syscon-wakeup = <&pericfg 0x420 3>; + #address-cells = <2>; + #size-cells = <2>; + }; + + u3phy0: usb-phy@11e40000 { + compatible = "mediatek,mt8192-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "okay"; + + u2port0: usb-phy@11e40000 { + reg = <0 0x11e40000 0 0x700>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@11e40700 { + reg = <0 0x11e40700 0 0x900>; + clocks = <&clk26m>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + audsys: syscon@11210000 { compatible = "mediatek,mt8192-audsys", "syscon"; reg = <0 0x11210000 0 0x1000>;