From patchwork Wed Sep 2 14:24:17 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Quadros X-Patchwork-Id: 52980 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-wi0-f200.google.com (mail-wi0-f200.google.com [209.85.212.200]) by patches.linaro.org (Postfix) with ESMTPS id EACD22300B for ; Wed, 2 Sep 2015 14:27:10 +0000 (UTC) Received: by wicuu12 with SMTP id uu12sf6722211wic.2 for ; Wed, 02 Sep 2015 07:27:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-type:sender:precedence :list-id:x-original-sender:x-original-authentication-results :mailing-list:list-post:list-help:list-archive:list-unsubscribe; bh=miF3F2KnynFa4eXtROrAiWv1j67G3xqgGu97YzxfHiI=; b=XtQ7BOofC0Pes0l6+6JeAfHg/UOiUZm8Q6mMdDsrszk8JcwD4stZzoK8vEFZa/vI87 a51gryQVtPDWItDzib2Cr6CvBmCvDWagtS7e+RoY+EqZxWtF9aPEFAvjter5jIVFV0L1 XD1gKkHX2eEVkPNR9BPzRUXbCtU0UN8zBP1leDUMUBTfD3DFqfAqDBbVlRLjUqoQowrh ZLrOzRaMCWUGCB9aqrB9KbwopGWV9RExwgH6Ifj4blnMEioGCgHLzDVrjDtY45QZDqgX BCjr4dNkItPx3i7f5Ylj9LQy0PGRbIKepHQac3D2faKtuZPYKDplqmnmqM+3tBJJL92u CzZA== X-Gm-Message-State: ALoCoQkI3aogbF6pJMkf1QG2nFcQxYdgXwuaZxGlPjFvALeEAc1sR9nW5SfQKgxPBQOV6AFgfnGd X-Received: by 10.112.139.65 with SMTP id qw1mr9116535lbb.24.1441204030119; Wed, 02 Sep 2015 07:27:10 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.152.1.199 with SMTP id 7ls71363lao.67.gmail; Wed, 02 Sep 2015 07:27:09 -0700 (PDT) X-Received: by 10.112.77.168 with SMTP id t8mr16135499lbw.70.1441204029948; Wed, 02 Sep 2015 07:27:09 -0700 (PDT) Received: from mail-la0-f53.google.com (mail-la0-f53.google.com. [209.85.215.53]) by mx.google.com with ESMTPS id rl10si19810087lbb.5.2015.09.02.07.27.09 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 02 Sep 2015 07:27:09 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) client-ip=209.85.215.53; Received: by lagj9 with SMTP id j9so8428081lag.2 for ; Wed, 02 Sep 2015 07:27:09 -0700 (PDT) X-Received: by 10.152.44.196 with SMTP id g4mr16061624lam.56.1441204029837; Wed, 02 Sep 2015 07:27:09 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.112.164.42 with SMTP id yn10csp616055lbb; Wed, 2 Sep 2015 07:27:08 -0700 (PDT) X-Received: by 10.66.100.234 with SMTP id fb10mr51533490pab.119.1441204028725; Wed, 02 Sep 2015 07:27:08 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id in13si35678352pac.223.2015.09.02.07.27.07; Wed, 02 Sep 2015 07:27:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755061AbbIBO1E (ORCPT + 28 others); Wed, 2 Sep 2015 10:27:04 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:52209 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754819AbbIBOYk (ORCPT ); Wed, 2 Sep 2015 10:24:40 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id t82EOZ6Z002465; Wed, 2 Sep 2015 09:24:35 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id t82EOZ40005023; Wed, 2 Sep 2015 09:24:35 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.224.2; Wed, 2 Sep 2015 09:24:34 -0500 Received: from rockdesk.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id t82EOPFP024150; Wed, 2 Sep 2015 09:24:32 -0500 From: Roger Quadros To: CC: , , , , , , , , Roger Quadros Subject: [PATCH v4 2/9] usb: dwc3: core.h: add some register definitions Date: Wed, 2 Sep 2015 17:24:17 +0300 Message-ID: <1441203864-15786-3-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1441203864-15786-1-git-send-email-rogerq@ti.com> References: <1441203864-15786-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.53 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Add OTG and GHWPARAMS6 register definitions Signed-off-by: Roger Quadros --- drivers/usb/dwc3/core.h | 82 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 5ca2b25..4b85330 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -173,6 +173,15 @@ #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1) #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) +/* Global Status Register */ +#define DWC3_GSTS_OTG_IP (1 << 10) +#define DWC3_GSTS_BC_IP (1 << 9) +#define DWC3_GSTS_ADP_IP (1 << 8) +#define DWC3_GSTS_HOST_IP (1 << 7) +#define DWC3_GSTS_DEVICE_IP (1 << 6) +#define DWC3_GSTS_CSR_TIMEOUT (1 << 5) +#define DWC3_GSTS_BUS_ERR_ADDR_VLD (1 << 4) + /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) @@ -234,6 +243,11 @@ #define DWC3_MAX_HIBER_SCRATCHBUFS 15 /* Global HWPARAMS6 Register */ +#define DWC3_GHWPARAMS6_BCSUPPORT (1 << 14) +#define DWC3_GHWPARAMS6_OTG3SUPPORT (1 << 13) +#define DWC3_GHWPARAMS6_ADPSUPPORT (1 << 12) +#define DWC3_GHWPARAMS6_HNPSUPPORT (1 << 11) +#define DWC3_GHWPARAMS6_SRPSUPPORT (1 << 10) #define DWC3_GHWPARAMS6_EN_FPGA (1 << 7) /* Device Configuration Register */ @@ -393,6 +407,74 @@ #define DWC3_DEPCMD_TYPE_BULK 2 #define DWC3_DEPCMD_TYPE_INTR 3 +/* OTG Configuration Register */ +#define DWC3_OCFG_DISPWRCUTTOFF (1 << 5) +#define DWC3_OCFG_HIBDISMASK (1 << 4) +#define DWC3_OCFG_SFTRSTMASK (1 << 3) +#define DWC3_OCFG_OTGVERSION (1 << 2) +#define DWC3_OCFG_HNPCAP (1 << 1) +#define DWC3_OCFG_SRPCAP (1 << 0) + +/* OTG CTL Register */ +#define DWC3_OCTL_OTG3GOERR (1 << 7) +#define DWC3_OCTL_PERIMODE (1 << 6) +#define DWC3_OCTL_PRTPWRCTL (1 << 5) +#define DWC3_OCTL_HNPREQ (1 << 4) +#define DWC3_OCTL_SESREQ (1 << 3) +#define DWC3_OCTL_TERMSELIDPULSE (1 << 2) +#define DWC3_OCTL_DEVSETHNPEN (1 << 1) +#define DWC3_OCTL_HSTSETHNPEN (1 << 0) + +/* OTG Event Register */ +#define DWC3_OEVT_DEVICEMODE (1 << 31) +#define DWC3_OEVT_XHCIRUNSTPSET (1 << 27) +#define DWC3_OEVT_DEVRUNSTPSET (1 << 26) +#define DWC3_OEVT_HIBENTRY (1 << 25) +#define DWC3_OEVT_CONIDSTSCHNG (1 << 24) +#define DWC3_OEVT_HRRCONFNOTIF (1 << 23) +#define DWC3_OEVT_HRRINITNOTIF (1 << 22) +#define DWC3_OEVT_ADEVIDLE (1 << 21) +#define DWC3_OEVT_ADEVBHOSTEND (1 << 20) +#define DWC3_OEVT_ADEVHOST (1 << 19) +#define DWC3_OEVT_ADEVHNPCHNG (1 << 18) +#define DWC3_OEVT_ADEVSRPDET (1 << 17) +#define DWC3_OEVT_ADEVSESSENDDET (1 << 16) +#define DWC3_OEVT_BDEVBHOSTEND (1 << 11) +#define DWC3_OEVT_BDEVHNPCHNG (1 << 10) +#define DWC3_OEVT_BDEVSESSVLDDET (1 << 9) +#define DWC3_OEVT_BDEVVBUSCHNG (1 << 8) +#define DWC3_OEVT_BSESSVLD (1 << 3) +#define DWC3_OEVT_HSTNEGSTS (1 << 2) +#define DWC3_OEVT_SESREQSTS (1 << 1) +#define DWC3_OEVT_ERROR (1 << 0) + +/* OTG Event Enable Register */ +#define DWC3_OEVTEN_XHCIRUNSTPSETEN (1 << 27) +#define DWC3_OEVTEN_DEVRUNSTPSETEN (1 << 26) +#define DWC3_OEVTEN_HIBENTRYEN (1 << 25) +#define DWC3_OEVTEN_CONIDSTSCHNGEN (1 << 24) +#define DWC3_OEVTEN_HRRCONFNOTIFEN (1 << 23) +#define DWC3_OEVTEN_HRRINITNOTIFEN (1 << 22) +#define DWC3_OEVTEN_ADEVIDLEEN (1 << 21) +#define DWC3_OEVTEN_ADEVBHOSTENDEN (1 << 20) +#define DWC3_OEVTEN_ADEVHOSTEN (1 << 19) +#define DWC3_OEVTEN_ADEVHNPCHNGEN (1 << 18) +#define DWC3_OEVTEN_ADEVSRPDETEN (1 << 17) +#define DWC3_OEVTEN_ADEVSESSENDDETEN (1 << 16) +#define DWC3_OEVTEN_BDEVHOSTENDEN (1 << 11) +#define DWC3_OEVTEN_BDEVHNPCHNGEN (1 << 10) +#define DWC3_OEVTEN_BDEVSESSVLDDETEN (1 << 9) +#define DWC3_OEVTEN_BDEVVBUSCHNGE (1 << 8) + +/* OTG Status Register */ +#define DWC3_OSTS_DEVRUNSTP (1 << 13) +#define DWC3_OSTS_XHCIRUNSTP (1 << 12) +#define DWC3_OSTS_PERIPHERALSTATE (1 << 4) +#define DWC3_OSTS_XHCIPRTPOWER (1 << 3) +#define DWC3_OSTS_BSESVLD (1 << 2) +#define DWC3_OSTS_VBUSVLD (1 << 1) +#define DWC3_OSTS_CONIDSTS (1 << 0) + /* Structures */ struct dwc3_trb;