| Message ID | cover.1689065318.git.quic_varada@quicinc.com |
|---|---|
| Headers | show |
| Series | Enable IPQ5332 USB2 | expand |
On 11/07/2023 10:51, Varadarajan Narayanan wrote: > Document the IPQ5332 dwc3 compatible. > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v1: > Add ipq5332 to interrupts sections Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On Tue, Jul 11, 2023 at 11:01:03AM +0200, Krzysztof Kozlowski wrote: > On 11/07/2023 10:51, Varadarajan Narayanan wrote: > > Add USB phy and controller nodes. > > > > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > > --- > > v1: > > Rename phy node > > I don't see any improvements. Will fix and post a new patch > > Change compatible from m31,ipq5332-usb-hsphy -> qcom,ipq5332-usb-hsphy > > Remove 'qscratch' from phy node > > Fix alignment and upper-case hex no.s > > Add clock definition for the phy > > Remove snps,ref-clock-period-ns as it is not used. dwc3_ref_clk_period() > > in dwc3/core.c takes the frequency from ref clock and calculates fladj > > as appropriate. > > --- > > arch/arm64/boot/dts/qcom/ipq5332.dtsi | 54 +++++++++++++++++++++++++++++++++++ > > 1 file changed, 54 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > > index 8bfc2db..c945ff6 100644 > > --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi > > +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi > > @@ -405,6 +405,60 @@ > > status = "disabled"; > > }; > > }; > > + > > + usbphy0: ipq5332-hsphy@7b000 { > > Node names should be generic. See also an explanation and list of > examples (not exhaustive) in DT specification: > https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation > > "phy" Will fix and post a new patch > > + compatible = "qcom,ipq5332-usb-hsphy"; > > + reg = <0x0007b000 0x12c>; > > + > > + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>; > > + clock-names = "cfg_ahb"; > > + > > + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; > > + > > + status = "disabled"; > > + }; > > + > > + usb2: usb2@8a00000 { > > It does not look like you tested the DTS against bindings. Please run > `make dtbs_check` (see > Documentation/devicetree/bindings/writing-schema.rst or > https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ > for instructions). 'make dtbs_check' passed. The '2' in 'usb2' is to indicate USB v2. There is one more USB v3 controller in this SoC. Hence, to differentiate between the two used 'usb2'. Hope that is ok. > > + compatible = "qcom,ipq5332-dwc3", "qcom,dwc3"; > > + > > No need for blank line. Will remove. Thanks Varada > > + reg = <0x08af8800 0x400>; > > + > > + interrupts = <GIC_SPI 62 IRQ_ > > > Best regards, > Krzysztof >
On 12/07/2023 13:28, Varadarajan Narayanan wrote: >>> + >>> + usb2: usb2@8a00000 { >> >> It does not look like you tested the DTS against bindings. Please run >> `make dtbs_check` (see >> Documentation/devicetree/bindings/writing-schema.rst or >> https://www.linaro.org/blog/tips-and-tricks-for-validating-devicetree-sources-with-the-devicetree-schema/ >> for instructions). > > 'make dtbs_check' passed. The '2' in 'usb2' is to indicate USB v2. > There is one more USB v3 controller in this SoC. Hence, to > differentiate between the two used 'usb2'. > > Hope that is ok. Nope, unfortunately it is not. Best regards, Krzysztof
On 11/07/2023 10:51, Varadarajan Narayanan wrote: > Document the M31 USB2 phy present in IPQ5332. > > Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> > Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> > --- > v3: > Incorporate review comments. Will bring in ipq5018 compatible > string while posting ipq5018 usb patchset. > > v1: > Rename qcom,m31.yaml -> qcom,ipq5332-usb-hsphy.yaml > Drop default binding "m31,usb-hsphy" > Add clock > Remove 'oneOf' from compatible > Remove 'qscratch' region from register space as it is not needed > Remove reset-names > Fix the example definition > --- > .../bindings/phy/qcom,ipq5332-usb-hsphy.yaml | 49 ++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > new file mode 100644 > index 0000000..2cfdd73 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,ipq5332-usb-hsphy.yaml > @@ -0,0 +1,49 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,ipq5332-usb-hsphy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: M31 (https://www.m31tech.com) USB PHY > + > +maintainers: > + - Sricharan Ramabadhran <quic_srichara@quicinc.com> > + - Varadarajan Narayanan <quic_varada@quicinc.org> I was wondering why I keep receiving delays/bounces for my emails in this thread... and here we have. Please correct your email. Best regards, Krzysztof