| Message ID | 20250320130054.4804-1-ansuelsmth@gmail.com |
|---|---|
| Headers | show |
| Series | airoha: en7581: clk cleanup + USB support | expand |
On Thu, Mar 20, 2025 at 02:00:26PM +0100, Christian Marangi wrote: > The Airoha AN7581 SoC have in the SCU register space particular > address that control how some peripheral are configured. > > These are toggeled in the System Status Register and are used to > toggle Serdes port for USB 3.0 mode or HSGMII, USB 3.0 mode or PCIe2 > or setup port for PCIe mode or Ethrnet mode (HSGMII/USXGMII). > > Modes are mutually exclusive and selecting one mode cause the > other feature to not work (example a mode in USB 3.0 cause PCIe > port 2 to not work) This depends also on what is physically > connected to the Hardware and needs to correctly reflect the > System Status Register bits. > > Special care is needed for PCIe port 0 in 2 line mode that > requires both WiFi1 and WiFi2 Serdes port set to PCIe0 2 Line > mode. > > Expose these configuration as an enum of strings in the SCU node and > also add dt-bindings header to reference each serdes port in DT. > > Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> > --- > .../bindings/clock/airoha,en7523-scu.yaml | 101 ++++++++++++++++-- > MAINTAINERS | 7 ++ > include/dt-bindings/soc/airoha,scu-ssr.h | 11 ++ > 3 files changed, 110 insertions(+), 9 deletions(-) > create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h > > diff --git a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml > index fe2c5c1baf43..637ce0e06619 100644 > --- a/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml > +++ b/Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml > @@ -9,6 +9,7 @@ title: EN7523 Clock > maintainers: > - Felix Fietkau <nbd@nbd.name> > - John Crispin <nbd@nbd.name> > + - Christian Marangi <ansuelsmth@gmail.com> > > description: | > This node defines the System Control Unit of the EN7523 SoC, > @@ -26,6 +27,23 @@ description: | > > The clocks are provided inside a system controller node. > > + The System Control Unit may also set different mode for the Serdes ports > + present on the SoC. > + > + These are toggeled in the System Status Register and are used to > + toggle Serdes port for USB 3.0 mode or HSGMII, USB 3.0 mode or PCIe2 > + or setup port for PCIe mode or Ethernet mode (HSGMII/USXGMII). > + > + Modes are mutually exclusive and selecting one mode cause the > + other feature to not work (example a mode in USB 3.0 cause PCIe > + port 2 to not work) This depends also on what is physically > + connected to the Hardware and needs to correctly reflect the > + System Status Register bits. > + > + Special care is needed for PCIe port 0 in 2 line mode that > + requires both WiFi1 and WiFi2 Serdes port set to PCIe0 2 Line > + mode. > + > properties: > compatible: > items: > @@ -49,6 +67,40 @@ properties: > description: ID of the controller reset line > const: 1 > > + airoha,serdes-wifi1: > + description: Configure the WiFi1 Serdes port > + $ref: /schemas/types.yaml#/definitions/string > + enum: > + - pcie0_x2 > + - pcie0_x1 > + - ethernet > + default: pcie0_x1 > + > + airoha,serdes-wifi2: > + description: Configure the WiFi2 Serdes port > + $ref: /schemas/types.yaml#/definitions/string > + enum: > + - pcie0_x2 > + - pcie1_x1 > + - ethernet > + default: pcie1_x1 > + > + airoha,serdes-usb1: > + description: Configure the USB1 Serdes port > + $ref: /schemas/types.yaml#/definitions/string > + enum: > + - usb3 > + - ethernet > + default: usb3 > + > + airoha,serdes-usb2: > + description: Configure the USB2 Serdes port > + $ref: /schemas/types.yaml#/definitions/string > + enum: > + - usb3 > + - pcie2_x1 > + default: usb3 Couldn't you make this a phy provider and use the mode flags in the phy cells? > + > required: > - compatible > - reg > @@ -64,6 +116,12 @@ allOf: > reg: > minItems: 2 > > + airoha,serdes-wifi1: false > + airoha,serdes-wifi2: false > + > + airoha,serdes-usb1: false > + airoha,serdes-usb2: false > + > '#reset-cells': false > > - if: > @@ -75,6 +133,24 @@ allOf: > reg: > maxItems: 1 > > + - if: > + properties: > + airoha,serdes-wifi1: > + const: pcie0_x2 This is also true if airoha,serdes-wifi1 is not present. Probably not what you intended. > + then: > + properties: > + airoha,serdes-wifi2: > + const: pcie0_x2 > + > + - if: > + properties: > + airoha,serdes-wifi2: > + const: pcie0_x2 > + then: > + properties: > + airoha,serdes-wifi1: > + const: pcie0_x2 > + > additionalProperties: false
This series implement all the changes required to correctly handle USB support for the Airoha EN7581 SoC. The first few patch are cleanup for the clock driver and the introduction of the SCU SSR SoC driver. The SoC always support USB 2.0 but for USB 3.0 it needs additional configuration for the Serdes port. Such port can be either configured for USB usage or for PCIe lines or HSGMII and these are configured in the SCU space. The xHCI USB is based on the Mediatek implementation but the PHY handling although conceptually similar, is indded different compared to Mediatek due to SSR checks and different port power up. The SSR driver expose an API to poll the current status of the Serdes port and the USB PHY driver validates it. Refer to the specific commit for additional info. Consider that there is currently an inconsistency as AN7581 and EN7581 refer to the same thing. This is due to the fact that the SoC born under EcoNet but then was acquired by Airoha. Changes v2: - Drop changes for simple-mfd - Rework PHY node structure to single node - Drop port-id property in favor of serdes-port and usb2-monitor-clock-sel - Make the SSR driver probe from the clock driver Christian Marangi (11): clk: en7523: convert driver to regmap API clk: en7523: generalize register clocks function dt-bindings: clock: en7523: add Documentation for Airoha AN7581 SCU SSR soc: airoha: add support for configuring SCU SSR Serdes port clk: en7523: define and register SoC SCU SSR driver for EN7581 soc: airoha: scu-ssr: expose API to read current Serdes Port mode dt-bindings: phy: Add documentation for Airoha AN7581 USB PHY phy: move Airoha PCIe PHY driver to dedicated directory phy: airoha: Add support for Airoha AN7581 USB PHY usb: host: add ARCH_AIROHA in XHCI MTK dependency arm64: dts: airoha: en7581: add USB nodes .../bindings/clock/airoha,en7523-scu.yaml | 101 +- .../bindings/phy/airoha,an7581-usb-phy.yaml | 83 ++ MAINTAINERS | 21 +- arch/arm64/boot/dts/airoha/en7581.dtsi | 49 + drivers/clk/clk-en7523.c | 340 +++-- drivers/phy/Kconfig | 11 +- drivers/phy/Makefile | 5 +- drivers/phy/airoha/Kconfig | 23 + drivers/phy/airoha/Makefile | 4 + drivers/phy/airoha/phy-airoha-pcie-regs.h | 494 +++++++ drivers/phy/airoha/phy-airoha-pcie.c | 1290 +++++++++++++++++ drivers/phy/airoha/phy-airoha-usb.c | 571 ++++++++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/airoha/Kconfig | 18 + drivers/soc/airoha/Makefile | 3 + drivers/soc/airoha/airoha-scu-ssr.c | 271 ++++ drivers/usb/host/Kconfig | 2 +- .../dt-bindings/phy/airoha,an7581-usb-phy.h | 11 + include/dt-bindings/soc/airoha,scu-ssr.h | 11 + include/linux/clk/clk-en7523.h | 10 + include/linux/soc/airoha/airoha-scu-ssr.h | 34 + 22 files changed, 3202 insertions(+), 152 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/airoha,an7581-usb-phy.yaml create mode 100644 drivers/phy/airoha/Kconfig create mode 100644 drivers/phy/airoha/Makefile create mode 100644 drivers/phy/airoha/phy-airoha-pcie-regs.h create mode 100644 drivers/phy/airoha/phy-airoha-pcie.c create mode 100644 drivers/phy/airoha/phy-airoha-usb.c create mode 100644 drivers/soc/airoha/Kconfig create mode 100644 drivers/soc/airoha/Makefile create mode 100644 drivers/soc/airoha/airoha-scu-ssr.c create mode 100644 include/dt-bindings/phy/airoha,an7581-usb-phy.h create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h create mode 100644 include/linux/clk/clk-en7523.h create mode 100644 include/linux/soc/airoha/airoha-scu-ssr.h