| Message ID | 20231020150022.48725-1-sebastian.reichel@collabora.com |
|---|---|
| Headers | show |
| Series | RK3588 USB3 host controller support | expand |
On Fri, Oct 20, 2023, Sebastian Reichel wrote: > On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and > requires two extra clocks to be enabled. Without these extra clocks > hot-plugging USB devices is broken. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > drivers/usb/dwc3/core.c | 28 ++++++++++++++++++++++++++++ > drivers/usb/dwc3/core.h | 4 ++++ > 2 files changed, 32 insertions(+) > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c > index 343d2570189f..639b768c3386 100644 > --- a/drivers/usb/dwc3/core.c > +++ b/drivers/usb/dwc3/core.c > @@ -854,8 +854,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc) > if (ret) > goto disable_ref_clk; > > + ret = clk_prepare_enable(dwc->utmi_clk); > + if (ret) > + goto disable_susp_clk; > + > + ret = clk_prepare_enable(dwc->pipe_clk); > + if (ret) > + goto disable_utmi_clk; > + > return 0; > > +disable_utmi_clk: > + clk_disable_unprepare(dwc->utmi_clk); > +disable_susp_clk: > + clk_disable_unprepare(dwc->susp_clk); > disable_ref_clk: > clk_disable_unprepare(dwc->ref_clk); > disable_bus_clk: > @@ -865,6 +877,8 @@ static int dwc3_clk_enable(struct dwc3 *dwc) > > static void dwc3_clk_disable(struct dwc3 *dwc) > { > + clk_disable_unprepare(dwc->pipe_clk); > + clk_disable_unprepare(dwc->utmi_clk); > clk_disable_unprepare(dwc->susp_clk); > clk_disable_unprepare(dwc->ref_clk); > clk_disable_unprepare(dwc->bus_clk); > @@ -1785,6 +1799,20 @@ static int dwc3_get_clocks(struct dwc3 *dwc) > } > } > > + /* specific to Rockchip RK3588 */ > + dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); > + if (IS_ERR(dwc->utmi_clk)) { > + return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), > + "could not get utmi clock\n"); > + } > + > + /* specific to Rockchip RK3588 */ > + dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); > + if (IS_ERR(dwc->pipe_clk)) { > + return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), > + "could not get pipe clock\n"); > + } > + > return 0; > } > > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h > index a69ac67d89fe..f5e6ae6e394e 100644 > --- a/drivers/usb/dwc3/core.h > +++ b/drivers/usb/dwc3/core.h > @@ -991,6 +991,8 @@ struct dwc3_scratchpad_array { > * @bus_clk: clock for accessing the registers > * @ref_clk: reference clock > * @susp_clk: clock used when the SS phy is in low power (S3) state > + * @utmi_clk: clock used for USB2 PHY communication > + * @pipe_clk: clock used for USB3 PHY communication > * @reset: reset control > * @regs: base address for our registers > * @regs_size: address space size > @@ -1156,6 +1158,8 @@ struct dwc3 { > struct clk *bus_clk; > struct clk *ref_clk; > struct clk *susp_clk; > + struct clk *utmi_clk; > + struct clk *pipe_clk; > > struct reset_control *reset; > > -- > 2.42.0 > Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com> BR, Thinh
Hi, This adds RK3588 USB3 host controller support. The same DT binding will be used for the two dual-role controllers, which are also DWC3 based, but using a different PHY and don't need the extra UTMI/PIPE clocks. The series has been tested with Radxa Rock 5B, which uses the controller for the upper USB3 port. The patch enabling &combphy2_psu and &usbhost3_0 for this board will be send separately once this series has been merged. Changes since PATCHv3: * https://lore.kernel.org/all/20231009172129.43568-1-sebastian.reichel@collabora.com/ * update binding, simplifying "rockchip,rk3568-dwc3" * update binding, no need to specify min/max items for "rockchip,rk3588-dwc3" * add driver inline comment, that "utmi" and "pipe" are RK3588 specific Changes since PATCHv2: * https://lore.kernel.org/all/20230720173643.69553-1-sebastian.reichel@collabora.com/ * update binding, so that "utmi" and "pipe" clocks may only be used on RK3588; at the same time do not allow "grf_clk" for RK3568, which does not have a GRF clock for USB3. Changes since PATCHv1: * https://lore.kernel.org/all/20230719174015.68153-1-sebastian.reichel@collabora.com/ * use same compatible for USB3 host and drd controllers (Krzysztof Kozlowski) * do not update reset-names (Krzysztof Kozlowski) - note: I dropped reset-names property, since there is only one reset line anyways. Binding could stay the same, since the reset-names property is optional * use "ref_clk", "suspend_clk" and "bus_clk" instead of "ref", "suspend" and "bus", so that they are the same as in RK3568 (Krzysztof Kozlowski) * rename handle name to "usb_host2_xhci" (Michael Riesch) * use RK356x style DWC3 binding instead of DWC3399 style - required adding an extra patch, so that the DWC3 core supports enabling the UTMI/PIPE clocks -- Sebastian Sebastian Reichel (3): dt-bindings: usb: add rk3588 compatible to rockchip,dwc3 usb: dwc3: add optional PHY interface clocks arm64: dts: rockchip: rk3588s: Add USB3 host controller .../bindings/usb/rockchip,dwc3.yaml | 60 +++++++++++++++++-- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++ drivers/usb/dwc3/core.c | 28 +++++++++ drivers/usb/dwc3/core.h | 4 ++ 4 files changed, 108 insertions(+), 5 deletions(-)