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[RFC,0/7] arm64: qcom: add Type-C Altmode support

Message ID 20230601-topic-sm8550-upstream-type-c-v1-0-d4d97b4d8bab@linaro.org
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Series arm64: qcom: add Type-C Altmode support | expand

Message

Neil Armstrong June 1, 2023, 2:07 p.m. UTC
This adds the missing bits to support the USB-C Altmode
support on SM8550.

These are the following changes since the previous SM8450 SoC:
- No more GLINK altmode events for USB only changes, only DP
- Type-C orientation is available on a PMIC signal connected
  to a GPIO line
- When altmode is disconnected, an 0xff mode event is sent.

In order to handle those changes, a new orientation-gpios property
is added to the usb-c connector bindings.
The 0xff altomode is translated as a SAFE type-c mux mode.

And in order to handle such info, we tie this to the UCSI connector
events to propagate the orientation to Type-C switches.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (7):
      dt-bindings: connector: usb-connector: add a gpio used to determine the Type-C port plug orientation
      soc: qcom: pmic_glink_altmode: handle safe mode when disconnect
      usb: ucsi: glink: use the connector orientation GPIO to provide switch events
      qcom: pmic_glink: enable altmode for SM8550
      arm64: dts: qcom: sm8550: add ports subnodes in usb/dp qmpphy node
      arm64: dts: qcom: sm8550-mtp: add pmic glink port/endpoints
      arm64: dts: qcom: sm8550-qrd: add pmic glink port/endpoints

 .../bindings/connector/usb-connector.yaml          |  5 ++
 arch/arm64/boot/dts/qcom/sm8550-mtp.dts            | 67 ++++++++++++++-
 arch/arm64/boot/dts/qcom/sm8550-qrd.dts            | 99 +++++++++++++++++++++-
 arch/arm64/boot/dts/qcom/sm8550.dtsi               | 26 ++++++
 drivers/soc/qcom/pmic_glink.c                      |  6 +-
 drivers/soc/qcom/pmic_glink_altmode.c              | 18 +++-
 drivers/usb/typec/ucsi/ucsi_glink.c                | 52 +++++++++++-
 7 files changed, 262 insertions(+), 11 deletions(-)
---
base-commit: f339b18115200db76b42475e44e3bc926e3ecab0
change-id: 20230601-topic-sm8550-upstream-type-c-e85b4d971450

Best regards,

Comments

Konrad Dybcio June 2, 2023, 9:16 a.m. UTC | #1
On 1.06.2023 16:07, Neil Armstrong wrote:
> Add the USB3+DP Combo QMP PHY port subnodes in the SM8550 SoC DTSI
> to avoid duplication in the devices DTs.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index b41b3981b3ce..ca2280041f83 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -2838,6 +2838,32 @@ usb_dp_qmpphy: phy@88e8000 {
>  			#phy-cells = <1>;
>  
>  			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +
> +					usb_dp_qmpphy_out: endpoint {
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +
> +					usb_dp_qmpphy_usb_ss_in: endpoint {
> +					};
> +				};
> +
> +				port@2 {
> +					reg = <2>;
> +
> +					usb_dp_qmpphy_dp_in: endpoint {
> +					};
> +				};
> +			};
>  		};
>  
>  		usb_1: usb@a6f8800 {
>