| Message ID | 20250506152350.3370291-2-va@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | [RESEND,1/3] spi: tegra210-quad: Add iommus property to DT bindings | expand |
On Tue, May 06, 2025 at 03:23:49PM +0000, Vishwaroop A wrote: > For Tegra234 devices, set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to > 99.99 MHz using PLLC as the parent clock. These frequencies enable > Quad IO reads at up to 99.99 MHz, the maximum achievable given PLL > and clock divider limitations. Introduce IOMMU property which is > needed for internal dma transfers. > > Signed-off-by: Vishwaroop A <va@nvidia.com> > --- > arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) I've applied this now. The remaining discussions on the bindings patch are details about how to deal with IOMMU on older platforms, but this patch in isolation is just adding standard properties. Thanks, Thierry
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 2601b43b2d8c..12fc850f9f5c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2948,6 +2948,11 @@ <&bpmp TEGRA234_CLK_QSPI0_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI0>; + iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; + assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI0_PM>; + assigned-clock-rates = <199999999 99999999>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; status = "disabled"; }; @@ -3031,6 +3036,11 @@ <&bpmp TEGRA234_CLK_QSPI1_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA234_RESET_QSPI1>; + iommus = <&smmu_niso1 TEGRA234_SID_QSPI1>; + assigned-clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>, + <&bpmp TEGRA234_CLK_QSPI1_PM>; + assigned-clock-rates = <199999999 99999999>; + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>; status = "disabled"; };
For Tegra234 devices, set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to 99.99 MHz using PLLC as the parent clock. These frequencies enable Quad IO reads at up to 99.99 MHz, the maximum achievable given PLL and clock divider limitations. Introduce IOMMU property which is needed for internal dma transfers. Signed-off-by: Vishwaroop A <va@nvidia.com> --- arch/arm64/boot/dts/nvidia/tegra234.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)