Message ID | 20250124105309.295769-4-quic_vdadhani@quicinc.com |
---|---|
State | New |
Headers | show |
Series | Add support to load QUP SE firmware from | expand |
On 24/01/2025 11:53, Viken Dadhaniya wrote: > .../devicetree/bindings/spi/qcom,spi-geni-qcom.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml > index 2e20ca313ec1..d0dd960ee12f 100644 > --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml > +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml > @@ -66,6 +66,12 @@ properties: > reg: > maxItems: 1 > > + qcom,xfer-mode: > + description: Set the value to 1 for non-GPI (FIFO/CPU DMA) mode and 3 for GPI DMA mode. > + The default mode is FIFO. > + $ref: /schemas/types.yaml#/definitions/uint32 Same concerns as for I2C, so discussion going there. Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml index 2e20ca313ec1..d0dd960ee12f 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -66,6 +66,12 @@ properties: reg: maxItems: 1 + qcom,xfer-mode: + description: Set the value to 1 for non-GPI (FIFO/CPU DMA) mode and 3 for GPI DMA mode. + The default mode is FIFO. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 3] + required: - compatible - clocks @@ -97,6 +103,7 @@ examples: interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; interconnect-names = "qup-core", "qup-config"; + qcom,xfer-mode = <1>; }; - |