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Thu, 2 Jan 2025 22:04:24 -0800 From: Vishwaroop A To: , , , , , , , , , CC: Subject: [PATCH V1 2/6] spi: tegra210-quad: Update dummy sequence configuration Date: Fri, 3 Jan 2025 06:04:03 +0000 Message-ID: <20250103060407.1064107-3-va@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250103060407.1064107-1-va@nvidia.com> References: <20250103060407.1064107-1-va@nvidia.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636C:EE_|BL3PR12MB6402:EE_ X-MS-Office365-Filtering-Correlation-Id: 74809e57-8ac4-4806-1576-08dd2bbc8091 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014|921020; X-Microsoft-Antispam-Message-Info: Tx8jC+ZumRFkmcBTfqctk1Sfii3jSl4n4pusxiYIEvsqxfPYQvOcMDq/f/Te9xhJtajP/1HHqZcuwSczY6UjAzT1l94uz8P4P86zoyjrLaVlrldGG+5hHSJsTk9M17NFZlzKEBRmjYMK49fbBXHzucSSK5gVxpxQgmAlyWXPSROakt8iyqmvBnYdHW1j2I8gDXYlC7VY4JHMoWrXNeNN1NjaqRlaFkVbU+iiRDNf+Yp1j1f/bz856CX9FZ+AluTz7fC7oXg7S2qD8gqgtZiEjFG5LhsqqEsOYTn9+YDtgNXO6QGL1PdoMK3DsR70ph0biIkJZXZ8xkUtNhYweu52WnNqSRlgBAhFTYlklPeF0XA07mGVq6+nlDyhRYmP8a3y696B24RMbunAjIRtku/FK8GgPjoXNZO110q6mlA8Y2fbtJQWu3Ox+j3pmtQ2Pm4sK6nPYRQwZgS+jgBzevM2kxJoMAbMW82YVeSP4csiVMOafVZPuuMYQYsgLe18Ywx2wrFnhxQquTXzWDPasc+ZyvziaW+57dPUDepQBfIUFxKPxEljOCKG1d1cg8kLoGXooEBUEVlfpIj6lJyoXODRtPsS+g3EbSYEgxM65/B4kwEkhFJrDUdDeE8YQN4L5vLM4/nbzgLQ87ie1DhKUAo5eRTqzg06I+p31URHmzpAWF5meoxc8YDKlAu+TLSFDpQri50rOPAQD0KpAV8gRgaTj4PbMtVtfYYFtIlnV/L8cpHtW2lIYzHv8JooMe213/QG1/tlBjJEJaEjgJ6aC/hsIAaW/U4A0AFBTKhotxFAklC4jTW4y5d1wEo/Z+e5IKNuDyTxnVjTAuQPuUNq24Mja7qT46kYBQdkNkU1JSwURMf8LgmxDw/QNqWWCdFsYGAdx+xmcmFa7jdZPs5slYhKvF3E4rHef6Whk/Re9/6DCWHwfbuSEQzectDwGO5gsx70vwMMv2UK9/IT3zKND0cbWBDCRCVGoo+i6DXCBmG01OssJnJe6CFJQkojjqBGVhzr2HBYpcljjoh6XxqzCKPumByhANyo2w8I17HKIYUt12HUlYI0tSr5aHH112rOgqAqfeGCRjbYVPRWzPhpmO1xWq8udEiJQo1lR02yALUwO2t18HBeob+pFQMRtDrTl3t4cyXDk3ZUL8M9CMy/lVljUbm1JasvXZzYlL5xukR7UA8FADU4Td/6yUTk8+wbVEVpsisj+c5fpiD9+ZrzQmGZFWQx9mWc6wi9zvHyiY1xJcluEAjJdKNUyOer9UAptYrQKutAQ2gGi0wgQFS9ANdFrohDrkg7p4ka1SZpM4ch6s2e80pkUfDd39Dd9OzioGtTwKmhFGYUlKZ6Q89VYJ1WhdB9U2QxZeVDDOGLEjRFoY2DlYdPBKWG7EA7gUJ1CUt/EAzGWVGfZrFEd8fqvZX20foQWA5Rrp5rpFQtius38sBCzrxgw25k/jxwyMh/ZX7gBzIf/fdM3O11aGd2RMmrh07CFG6cmlx5SoywKmUuiUQ= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014)(921020); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2025 06:04:36.6066 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74809e57-8ac4-4806-1576-08dd2bbc8091 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6402 Adding support for the dummy sequence configuration. The dummy sequence introduces a delay between the command and the data phases of a transfer. This delay, measured in clock cycles, allows the slave device to prepare for data transmission, ensuring data integrity and proper synchronization. Change-Id: I4dc347a247830452754f83e88aa95a7d231722cd Signed-off-by: Vishwaroop A --- drivers/spi/spi-tegra210-quad.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-tegra210-quad.c b/drivers/spi/spi-tegra210-quad.c index 08e49a876894..02478e8efc8f 100644 --- a/drivers/spi/spi-tegra210-quad.c +++ b/drivers/spi/spi-tegra210-quad.c @@ -22,6 +22,7 @@ #include #include #include +#include #define QSPI_COMMAND1 0x000 #define QSPI_BIT_LENGTH(x) (((x) & 0x1f) << 0) @@ -156,10 +157,14 @@ #define DATA_DIR_RX BIT(1) #define QSPI_DMA_TIMEOUT (msecs_to_jiffies(1000)) -#define DEFAULT_QSPI_DMA_BUF_LEN (64 * 1024) -#define CMD_TRANSFER 0 -#define ADDR_TRANSFER 1 -#define DATA_TRANSFER 2 +#define DEFAULT_QSPI_DMA_BUF_LEN SZ_64K + +enum tegra_qspi_transfer_type { + CMD_TRANSFER = 0, + ADDR_TRANSFER = 1, + DUMMY_TRANSFER = 2, + DATA_TRANSFER = 3 +}; struct tegra_qspi_soc_data { bool has_dma; @@ -1089,6 +1094,13 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, xfer->len); address_value = *((const u32 *)(xfer->tx_buf)); break; + case DUMMY_TRANSFER: + if (xfer->dummy_data) { + tqspi->dummy_cycles = xfer->len * 8 / xfer->tx_nbits; + break; + } + transfer_phase++; + fallthrough; case DATA_TRANSFER: /* Program Command, Address value in register */ tegra_qspi_writel(tqspi, cmd_value, QSPI_CMB_SEQ_CMD); @@ -1300,7 +1312,9 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, list_for_each_entry(xfer, &msg->transfers, transfer_list) { transfer_count++; } - if (!tqspi->soc_data->cmb_xfer_capable || transfer_count != 3) + if (!tqspi->soc_data->cmb_xfer_capable) + return false; + if (transfer_count > 4 || transfer_count < 3) return false; xfer = list_first_entry(&msg->transfers, typeof(*xfer), transfer_list); @@ -1310,6 +1324,13 @@ static bool tegra_qspi_validate_cmb_seq(struct tegra_qspi *tqspi, if (xfer->len > 4 || xfer->len < 3) return false; xfer = list_next_entry(xfer, transfer_list); + if (transfer_count == 4) { + if (xfer->dummy_data != 1) + return false; + if ((xfer->len * 8 / xfer->tx_nbits) > QSPI_DUMMY_CYCLES_MAX) + return false; + xfer = list_next_entry(xfer, transfer_list); + } if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) return false;