From patchwork Thu Jul 25 13:56:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Usyskin X-Patchwork-Id: 814837 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 539F519D074 for ; Thu, 25 Jul 2024 14:06:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721916373; cv=none; b=BnO+5QSulLgku364P8PCBIjriP91H/p6ll8hjvmyfejtMigR55coKBPkAEwep8CcKdnrjiMzqpiBjLDR11FYhEqJMC5q32hm0/uPlhwdWZ+yOHi+YIoyJYnYJuCit3T47UeTDA31pkfo5r/n/eeXdVtBggfRXrC7Pc2QNpF7biQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1721916373; c=relaxed/simple; bh=ykvhi9CLDv624qgten1HNwsh5CZkKKRX9KCLAGda0l8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=t0uz9jdHtxVU5UkQfgcXYw8KMR38ycA4DPIQIu9SLPgFnbOo/i+PnUp0xTBh/BjGM6b2KxLcO0HghAKvUC9yHY2AiWwQCCoUWVgajE6kTqTH2zEcpgaW5Y0BocxWD0MpsqfXngK+AffjBPFdegPxDZvSEY4akslcata/raiJc6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=LmMEVh2I; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="LmMEVh2I" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1721916373; x=1753452373; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ykvhi9CLDv624qgten1HNwsh5CZkKKRX9KCLAGda0l8=; b=LmMEVh2IOARpnEojFabC8RmMsK+0ynIQMkz7f2n9N7FZ07wq3A15DwqZ w297X8n1w4wAeQ+SHiKZLEEi386y3B+c/GER09qWOZbdqOZm+3M8WX8NT bJszMOdI0ywHJ1BWHT41F9uPXSSQz8GuVGQv+phSQaWdWFrfty+h8/69d SUGJrDRu30R+L/dnYT9cJpEqSEbOzyt3XGeCrkCpxEVLuIB/Lv9ld8LsK 48fUT4yKXSoExla4lbKueA9cKnVS1/YcF62VpTh5VtIUN4WRRxQEPqCPR RTSWWy/gIr+EY3lFzcu90Yvzkd4s5RJADvaFo0cbhIq9bm1VO+urCYek2 A==; X-CSE-ConnectionGUID: a6Imt6x2SBi2C6CpA6Ygsw== X-CSE-MsgGUID: /DChvYSRRTyJ9ze9qArSfw== X-IronPort-AV: E=McAfee;i="6700,10204,11144"; a="19504941" X-IronPort-AV: E=Sophos;i="6.09,236,1716274800"; d="scan'208";a="19504941" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2024 07:06:12 -0700 X-CSE-ConnectionGUID: w2prjSJfTQqnE2MDYMt/eA== X-CSE-MsgGUID: Ie87jppNRguJzuLI+ImUKg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,236,1716274800"; d="scan'208";a="53007828" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Jul 2024 07:06:04 -0700 From: Alexander Usyskin To: Mark Brown , Lucas De Marchi , Oded Gabbay , =?utf-8?q?Thomas_Hellstr=C3=B6m?= , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Jani Nikula , Joonas Lahtinen , Rodrigo Vivi , Tvrtko Ursulin Cc: Tomas Winkler , Alexander Usyskin , Vitaly Lubart , intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-spi@vger.kernel.org, intel-gfx@lists.freedesktop.org Subject: [PATCH v3 09/12] drm/i915/spi: add intel_spi_region map Date: Thu, 25 Jul 2024 16:56:54 +0300 Message-Id: <20240725135657.1061836-10-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240725135657.1061836-1-alexander.usyskin@intel.com> References: <20240725135657.1061836-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Tomas Winkler Add the dGFX spi region map and convey it via auxiliary device to the spi child device. CC: Rodrigo Vivi CC: Lucas De Marchi Signed-off-by: Tomas Winkler Signed-off-by: Alexander Usyskin --- drivers/gpu/drm/i915/spi/intel_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/spi/intel_spi.c b/drivers/gpu/drm/i915/spi/intel_spi.c index 17e4c7861ef5..8dd4065551e2 100644 --- a/drivers/gpu/drm/i915/spi/intel_spi.c +++ b/drivers/gpu/drm/i915/spi/intel_spi.c @@ -11,6 +11,13 @@ #define GEN12_GUNIT_SPI_SIZE 0x80 +static const struct intel_dg_spi_region regions[INTEL_DG_SPI_REGIONS] = { + [0] = { .name = "DESCRIPTOR", }, + [2] = { .name = "GSC", }, + [11] = { .name = "OptionROM", }, + [12] = { .name = "DAM", }, +}; + static void i915_spi_release_dev(struct device *dev) { } @@ -31,6 +38,7 @@ void intel_spi_init(struct drm_i915_private *dev_priv) spi->bar.end = spi->bar.start + GEN12_GUNIT_SPI_SIZE - 1; spi->bar.flags = IORESOURCE_MEM; spi->bar.desc = IORES_DESC_NONE; + spi->regions = regions; aux_dev->name = "spi"; aux_dev->id = (pci_domain_nr(pdev->bus) << 16) |