From patchwork Thu May 16 18:18:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eddie James X-Patchwork-Id: 797462 Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A5FF156642; Thu, 16 May 2024 18:19:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.163.156.1 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883570; cv=none; b=eHYFgjo6QGEEtlP/zr1tgFxJYnq284wqYlctxhBGSy541v+h+TbvKV6GEJbi4gvA0/B+/ZTeA4pefwFRgtK6XMt6qw642M51/IZ+nvxKNJJ6dcWsZ41Rz4xEjKBDTyjTmJk9Q78tzq/SUiUB7JYACGSTi36Lz4hZWJQxKYY9A6U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1715883570; c=relaxed/simple; bh=28Gfq7n26fRHxuUeS4aQmeyrgTs1A+//LqHpjvdZ47s=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=R+njMuaz8sD4Wp6VNR95PBsOn22cfN22UzB38IiCcr82TOIOsh7aUcY4P+qlMMWvPAmiBhqSOMroP3BfZ8YcWhTomVg7VYqxtKDwcyg9dx1CrO1/yTp+xKq+nVw9zfTX4ML/3s6EFHJmuSmxIgKP1yau2DWFbJA0+kNF68LFZZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com; spf=pass smtp.mailfrom=linux.ibm.com; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b=LYGycENy; arc=none smtp.client-ip=148.163.156.1 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.ibm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ibm.com header.i=@ibm.com header.b="LYGycENy" Received: from pps.filterd (m0353727.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 44GGlkYQ024026; Thu, 16 May 2024 18:19:12 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=oHKlxwrlNdF8PlHD5y5HFMOj3x1VaBvrVhlzZpRcYr8=; b=LYGycENy4QH0LuBilPDzr5gzmJ66DMo8gaB6ilRVLkDXj7Uk5rV9XltTHRjO8cj+ULTA hGE6K4LERPt4ARhDKuBw63pKpKf0ku/aCc7q18xAPKvI/o+Wx6CEU4m8imqLSUPjd4qN LGOvH6KC0vKRIiQdHJyf4tIyL1yDhSKlr6eYjVtjlC2A8RCe3Alnv0nI+nC1KPshZ8m/ Fah+hNtoFFfjqDvpGENK8CJDJcagr6MN4H/BeCscaCBjfdNxjJ/sCrJLyPBxS4Kykq/0 t+FEiLpbhRVmB9VOzI2iWcjH7NpNEuUUJZ2l2yt6J/FVMjapD+GOJZRgHkymvXI696Zm tg== Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3y5nycr8d5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:11 +0000 Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 44GGKNh8006073; Thu, 16 May 2024 18:19:10 GMT Received: from smtprelay05.dal12v.mail.ibm.com ([172.16.1.7]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 3y2nq331vn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 May 2024 18:19:10 +0000 Received: from smtpav05.dal12v.mail.ibm.com (smtpav05.dal12v.mail.ibm.com [10.241.53.104]) by smtprelay05.dal12v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 44GIJ8I913566572 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 16 May 2024 18:19:10 GMT Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 372DF5806F; Thu, 16 May 2024 18:19:08 +0000 (GMT) Received: from smtpav05.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EA9545807E; Thu, 16 May 2024 18:19:07 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.107.19]) by smtpav05.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 16 May 2024 18:19:07 +0000 (GMT) From: Eddie James To: linux-fsi@lists.ozlabs.org Cc: linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org, linux-spi@vger.kernel.org, broonie@kernel.org, andi.shyti@kernel.org, joel@jms.id.au, alistair@popple.id.au, jk@ozlabs.org, andrew@codeconstruct.com.au, linux-aspeed@lists.ozlabs.org, eajames@linux.ibm.com Subject: [PATCH v3 02/40] fsi: Move slave definitions to fsi-slave.h Date: Thu, 16 May 2024 13:18:29 -0500 Message-Id: <20240516181907.3468796-3-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240516181907.3468796-1-eajames@linux.ibm.com> References: <20240516181907.3468796-1-eajames@linux.ibm.com> Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: 9ahhNrsrXLPZwHiaLLpIZK0eSJdPoh2d X-Proofpoint-ORIG-GUID: 9ahhNrsrXLPZwHiaLLpIZK0eSJdPoh2d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2405010000 definitions=main-2405160132 Master drivers may need access to the slave definitions. Signed-off-by: Eddie James --- drivers/fsi/fsi-core.c | 35 ----------------- drivers/fsi/fsi-slave.h | 84 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 84 insertions(+), 35 deletions(-) diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c index 097d5a780264c..7bf0c96fc0172 100644 --- a/drivers/fsi/fsi-core.c +++ b/drivers/fsi/fsi-core.c @@ -45,41 +45,6 @@ static const int engine_page_size = 0x400; -#define FSI_SLAVE_BASE 0x800 - -/* - * FSI slave engine control register offsets - */ -#define FSI_SMODE 0x0 /* R/W: Mode register */ -#define FSI_SISC 0x8 /* R/W: Interrupt condition */ -#define FSI_SSTAT 0x14 /* R : Slave status */ -#define FSI_SLBUS 0x30 /* W : LBUS Ownership */ -#define FSI_LLMODE 0x100 /* R/W: Link layer mode register */ - -/* - * SMODE fields - */ -#define FSI_SMODE_WSC 0x80000000 /* Warm start done */ -#define FSI_SMODE_ECRC 0x20000000 /* Hw CRC check */ -#define FSI_SMODE_SID_SHIFT 24 /* ID shift */ -#define FSI_SMODE_SID_MASK 3 /* ID Mask */ -#define FSI_SMODE_ED_SHIFT 20 /* Echo delay shift */ -#define FSI_SMODE_ED_MASK 0xf /* Echo delay mask */ -#define FSI_SMODE_SD_SHIFT 16 /* Send delay shift */ -#define FSI_SMODE_SD_MASK 0xf /* Send delay mask */ -#define FSI_SMODE_LBCRR_SHIFT 8 /* Clk ratio shift */ -#define FSI_SMODE_LBCRR_MASK 0xf /* Clk ratio mask */ - -/* - * SLBUS fields - */ -#define FSI_SLBUS_FORCE 0x80000000 /* Force LBUS ownership */ - -/* - * LLMODE fields - */ -#define FSI_LLMODE_ASYNC 0x1 - #define FSI_SLAVE_SIZE_23b 0x800000 static DEFINE_IDA(master_ida); diff --git a/drivers/fsi/fsi-slave.h b/drivers/fsi/fsi-slave.h index 1d63a585829dd..dba65bd4e083f 100644 --- a/drivers/fsi/fsi-slave.h +++ b/drivers/fsi/fsi-slave.h @@ -7,6 +7,90 @@ #include #include +#define FSI_SLAVE_BASE 0x800 + +/* + * FSI slave engine control register offsets + */ +#define FSI_SMODE 0x0 /* R/W: Mode register */ +#define FSI_SISC 0x8 /* R : Interrupt condition */ +#define FSI_SCISC 0x8 /* C : Clear interrupt condition */ +#define FSI_SISM 0xc /* R/W: Interrupt mask */ +#define FSI_SISS 0x10 /* R : Interrupt status */ +#define FSI_SSISM 0x10 /* S : Set interrupt mask */ +#define FSI_SCISM 0x14 /* C : Clear interrupt mask */ +#define FSI_SSTAT 0x14 /* R : Slave status */ +#define FSI_SI1S 0x1c /* R : Slave interrupt 1 status */ +#define FSI_SSI1M 0x1c /* S : Set slave interrupt 1 mask */ +#define FSI_SCI1M 0x20 /* C : Clear slave interrupt 1 mask */ +#define FSI_SLBUS 0x30 /* W : LBUS Ownership */ +#define FSI_SRSIC0 0x68 /* C : Clear remote interrupt condition */ +#define FSI_SRSIC4 0x6c /* C : Clear remote interrupt condition */ +#define FSI_SRSIM0 0x70 /* R/W: Remote interrupt mask */ +#define FSI_SRSIM4 0x74 /* R/W: Remote interrupt mask */ +#define FSI_SRSIS0 0x78 /* R : Remote interrupt status */ +#define FSI_SRSIS4 0x7c /* R : Remote interrupt status */ +#define FSI_LLMODE 0x100 /* R/W: Link layer mode register */ + +/* + * SMODE fields + */ +#define FSI_SMODE_WSC 0x80000000 /* Warm start done */ +#define FSI_SMODE_ECRC 0x20000000 /* Hw CRC check */ +#define FSI_SMODE_SID_SHIFT 24 /* ID shift */ +#define FSI_SMODE_SID_MASK 3 /* ID Mask */ +#define FSI_SMODE_ED_SHIFT 20 /* Echo delay shift */ +#define FSI_SMODE_ED_MASK 0xf /* Echo delay mask */ +#define FSI_SMODE_SD_SHIFT 16 /* Send delay shift */ +#define FSI_SMODE_SD_MASK 0xf /* Send delay mask */ +#define FSI_SMODE_LBCRR_SHIFT 8 /* Clk ratio shift */ +#define FSI_SMODE_LBCRR_MASK 0xf /* Clk ratio mask */ + +/* + * SISS fields + */ +#define FSI_SISS_CRC_ERROR BIT(31) +#define FSI_SISS_PROTO_ERROR BIT(30) +#define FSI_SISS_LBUS_PARITY_ERROR BIT(29) +#define FSI_SISS_LBUS_PROTO_ERROR BIT(28) +#define FSI_SISS_ACCESS_ERROR BIT(27) +#define FSI_SISS_LBUS_OWNERSHIP_ERROR BIT(26) +#define FSI_SISS_LBUS_OWNERSHIP_CHANGE BIT(25) +#define FSI_SISS_ASYNC_MODE_ERROR BIT(14) +#define FSI_SISS_OPB_ACCESS_ERROR BIT(13) +#define FSI_SISS_OPB_FENCED BIT(12) +#define FSI_SISS_OPB_PARITY_ERROR BIT(11) +#define FSI_SISS_OPB_PROTO_ERROR BIT(10) +#define FSI_SISS_OPB_TIMEOUT BIT(9) +#define FSI_SISS_OPB_ERROR_ACK BIT(8) +#define FSI_SISS_MFSI_MASTER_ERROR BIT(3) +#define FSI_SISS_MFSI_PORT_ERROR BIT(2) +#define FSI_SISS_MFSI_HP BIT(1) +#define FSI_SISS_MFSI_CR_PARITY_ERROR BIT(0) +#define FSI_SISS_ALL 0xfe007f00 + +/* + * SI1S fields + */ +#define FSI_SI1S_SLAVE_BIT 31 +#define FSI_SI1S_SHIFT_BIT 30 +#define FSI_SI1S_SCOM_BIT 29 +#define FSI_SI1S_SCRATCH_BIT 28 +#define FSI_SI1S_I2C_BIT 27 +#define FSI_SI1S_SPI_BIT 26 +#define FSI_SI1S_SBEFIFO_BIT 25 +#define FSI_SI1S_MBOX_BIT 24 + +/* + * SLBUS fields + */ +#define FSI_SLBUS_FORCE 0x80000000 /* Force LBUS ownership */ + +/* + * LLMODE fields + */ +#define FSI_LLMODE_ASYNC 0x1 + struct fsi_master; struct fsi_slave {