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Thu, 25 Apr 2024 21:37:11 +0000 Received: from smtpav04.wdc07v.mail.ibm.com (smtpav04.wdc07v.mail.ibm.com [10.39.53.231]) by smtprelay04.wdc07v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 43PLb7Z728836522 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 25 Apr 2024 21:37:09 GMT Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 958A358060; Thu, 25 Apr 2024 21:37:07 +0000 (GMT) Received: from smtpav04.wdc07v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E3A4D58045; Thu, 25 Apr 2024 21:37:06 +0000 (GMT) Received: from slate16.aus.stglabs.ibm.com (unknown [9.61.133.34]) by smtpav04.wdc07v.mail.ibm.com (Postfix) with ESMTP; Thu, 25 Apr 2024 21:37:06 +0000 (GMT) From: Eddie James To: linux-aspeed@lists.ozlabs.org Cc: eajames@linux.ibm.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-fsi@lists.ozlabs.org, linux-spi@vger.kernel.org, linux-i2c@vger.kernel.org, lakshmiy@us.ibm.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, joel@jms.id.au, andrew@codeconstruct.com.au Subject: [PATCH v3 06/14] dt-bindings: fsi: Document the FSI controller common properties Date: Thu, 25 Apr 2024 16:36:53 -0500 Message-Id: <20240425213701.655540-7-eajames@linux.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240425213701.655540-1-eajames@linux.ibm.com> References: <20240425213701.655540-1-eajames@linux.ibm.com> X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: 5TDr2M2OzFukzCAhHnaCDew7u399F6f1 X-Proofpoint-GUID: 5TDr2M2OzFukzCAhHnaCDew7u399F6f1 X-Proofpoint-UnRewURL: 0 URL was un-rewritten Precedence: bulk X-Mailing-List: linux-spi@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1011,Hydra:6.0.650,FMLib:17.11.176.26 definitions=2024-04-25_21,2024-04-25_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 clxscore=1015 mlxscore=0 bulkscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2404010000 definitions=main-2404250157 Since there are multiple FSI controllers documented, the common properties should be documented separately and then referenced from the specific controller documentation. Signed-off-by: Eddie James --- .../bindings/fsi/fsi-controller.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/fsi/fsi-controller.yaml diff --git a/Documentation/devicetree/bindings/fsi/fsi-controller.yaml b/Documentation/devicetree/bindings/fsi/fsi-controller.yaml new file mode 100644 index 000000000000..9e917295996d --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/fsi-controller.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/fsi-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FSI Controller Common Properties + +maintainers: + - Eddie James + +description: + FSI (FRU (Field Replaceable Unit) Service Interface) is a two wire bus. The + FSI bus is connected to a CFAM (Common FRU Access Macro) which contains + various engines such as I2C controllers, SPI controllers, etc. + +properties: + "#address-cells": + const: 2 + + "#size-cells": + const: 0 + + no-scan-on-init: + $ref: /schemas/types.yaml#/definitions/flag + description: + The FSI controller cannot scan the bus during initialization. + +patternProperties: + "cfam@[0-9a-f],[0-9a-f]": + type: object + properties: + chip-id: + $ref: /schemas/types.yaml#/definitions/uint32 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + required: + - reg + + additionalProperties: true + +additionalProperties: true + +examples: + - | + fsi@3400 { + #address-cells = <2>; + #size-cells = <0>; + compatible = "fsi-controller"; + reg = <0x3400 0x400>; + + cfam@0,0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0 0>; + }; + };