From patchwork Thu Jan 4 13:01:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harald Mommer X-Patchwork-Id: 760110 Received: from refb02.tmes.trendmicro.eu (refb02.tmes.trendmicro.eu [18.185.115.60]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0107C22305 for ; Thu, 4 Jan 2024 13:13:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=opensynergy.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=opensynergy.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=opensynergy.com header.i=@opensynergy.com header.b="wOf4cC/t" Received: from 104.47.7.169_.trendmicro.com (unknown [172.21.19.34]) by refb02.tmes.trendmicro.eu (Postfix) with ESMTPS id 55D3B10A32985 for ; Thu, 4 Jan 2024 13:01:53 +0000 (UTC) Received: from 104.47.7.169_.trendmicro.com (unknown [172.21.176.220]) by repost01.tmes.trendmicro.eu (Postfix) with SMTP id 7C7E210000C35; Thu, 4 Jan 2024 13:01:46 +0000 (UTC) X-TM-MAIL-RECEIVED-TIME: 1704373306.074000 X-TM-MAIL-UUID: 5474ea3e-5a98-4133-a7e1-e61acef30fb5 Received: from DEU01-BE0-obe.outbound.protection.outlook.com (unknown [104.47.7.169]) by repre01.tmes.trendmicro.eu (Trend Micro Email Security) with ESMTPS id 123591000040D; Thu, 4 Jan 2024 13:01:46 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IMTOQVH5GgGvmKH0ocYlm8p9atXFSedlLCoue4ZpWX2ec1VWAAgpvrTVWeSkf/MnZS8oKM6yHz6ztlmlL8j+Vp67Rb2DZ7fp4ItK7C1pQL+cPAlw7/sdcVBxnSF/h/JmGn8NXRSlVbIUbh/BDC048sCkOMKl8qQRzkhlg1DdFEjpnfTY4r9PMXqYYuaKcDLPLcoZUGWsGPrzcyrG02JguO+T81gGDwKtrpzVAYHbI9a70LHdexiYcbhcIKgNCNcy8kymRi00+6Oovgmrf2hj36ZSGHD7RUf4M0lVWlw7nzrLDcdAXy2FbNBEX0osc4c+V5CL3V2VUMp1WisozpM0rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=k373ENbKKgZEygbJ2ZAkGzkQCJqpH/pxUPIlD6aCUPM=; b=YwXq/S1eIESO80Qi3ZVlHgxxakgZf54FAIaBcxguNcWhzHBxtxOEVeAQk9yLzrDCBk8KfW+nNqekElVccaN1JeC3QileZCqbjR9TMg8RHfo10HgUyB1CrXbhWlF1p1pRMCXxxTn82SqUL2OSHgAHf9N23W5RsaSSLDc9MnXRfj2a0h1TbufqGhYipU3NIEUa6iWW7Q733YylF0YFZx/APl2/S1zY1zrqdp+ZwsBVxJI2YfSB3AU6J8uBTm5KyAANEI2xQ7yX4EOXhweMcanoFbOyGfKt5vBsv7vc2CA/0L9ZB+YPX+wkmvdl3L9Gbc1pr8nsNA+/uAu+GaUlulx/bg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 217.66.60.4) smtp.rcpttodomain=kernel.org smtp.mailfrom=opensynergy.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=opensynergy.com; dkim=none (message not signed); arc=none (0) X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 217.66.60.4) smtp.mailfrom=opensynergy.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=opensynergy.com; Received-SPF: Pass (protection.outlook.com: domain of opensynergy.com designates 217.66.60.4 as permitted sender) receiver=protection.outlook.com; client-ip=217.66.60.4; helo=SR-MAIL-03.open-synergy.com; pr=C From: Harald Mommer To: virtio-dev@lists.oasis-open.org, Haixu Cui , Mark Brown , Viresh Kumar , linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_ztu@quicinc.com, Matti Moell , Mikhail Golubev , Harald Mommer Subject: [RFC PATCH v2 2/3] virtio-spi: Add virtio-spi.h (V10 draft specification). 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The header file is compliant to the virtio SPI draft specification V10. Signed-off-by: Harald Mommer Reviewed-by: Viresh Kumar --- include/uapi/linux/virtio_spi.h | 185 ++++++++++++++++++++++++++++++++ 1 file changed, 185 insertions(+) create mode 100644 include/uapi/linux/virtio_spi.h diff --git a/include/uapi/linux/virtio_spi.h b/include/uapi/linux/virtio_spi.h new file mode 100644 index 000000000000..d56843fcb2ec --- /dev/null +++ b/include/uapi/linux/virtio_spi.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2023 OpenSynergy GmbH + */ +#ifndef _LINUX_VIRTIO_VIRTIO_SPI_H +#define _LINUX_VIRTIO_VIRTIO_SPI_H + +#include +#include +#include +#include + +/* Sample data on trailing clock edge */ +#define VIRTIO_SPI_CPHA (1 << 0) +/* Clock is high when IDLE */ +#define VIRTIO_SPI_CPOL (1 << 1) +/* Chip Select is active high */ +#define VIRTIO_SPI_CS_HIGH (1 << 2) +/* Transmit LSB first */ +#define VIRTIO_SPI_MODE_LSB_FIRST (1 << 3) +/* Loopback mode */ +#define VIRTIO_SPI_MODE_LOOP (1 << 4) + +/* + * All config fields are read-only for the Virtio SPI driver + * + * @cs_max_number: maximum number of chipselect the host SPI controller + * supports. + * @cs_change_supported: indicates if the host SPI controller supports to toggle + * chipselect after each transfer in one message: + * 0: unsupported, chipselect will be kept in active state throughout the + * message transaction; + * 1: supported. + * Note: Message here contains a sequence of SPI transfers. + * @tx_nbits_supported: indicates the supported number of bit for writing: + * bit 0: DUAL (2-bit transfer), 1 for supported + * bit 1: QUAD (4-bit transfer), 1 for supported + * bit 2: OCTAL (8-bit transfer), 1 for supported + * other bits are reserved as 0, 1-bit transfer is always supported. + * @rx_nbits_supported: indicates the supported number of bit for reading: + * bit 0: DUAL (2-bit transfer), 1 for supported + * bit 1: QUAD (4-bit transfer), 1 for supported + * bit 2: OCTAL (8-bit transfer), 1 for supported + * other bits are reserved as 0, 1-bit transfer is always supported. + * @bits_per_word_mask: mask indicating which values of bits_per_word are + * supported. If not set, no limitation for bits_per_word. + * @mode_func_supported: indicates the following features are supported or not: + * bit 0-1: CPHA feature + * 0b00: invalid, should support as least one CPHA setting + * 0b01: supports CPHA=0 only + * 0b10: supports CPHA=1 only + * 0b11: supports CPHA=0 and CPHA=1. + * bit 2-3: CPOL feature + * 0b00: invalid, should support as least one CPOL setting + * 0b01: supports CPOL=0 only + * 0b10: supports CPOL=1 only + * 0b11: supports CPOL=0 and CPOL=1. + * bit 4: chipselect active high feature, 0 for unsupported and 1 for + * supported, chipselect active low should always be supported. + * bit 5: LSB first feature, 0 for unsupported and 1 for supported, + * MSB first should always be supported. + * bit 6: loopback mode feature, 0 for unsupported and 1 for supported, + * normal mode should always be supported. + * @max_freq_hz: the maximum clock rate supported in Hz unit, 0 means no + * limitation for transfer speed. + * @max_word_delay_ns: the maximum word delay supported in ns unit, + * 0 means word delay feature is unsupported. + * Note: Just as one message contains a sequence of transfers, + * one transfer may contain a sequence of words. + * @max_cs_setup_ns: the maximum delay supported after chipselect is asserted, + * in ns unit, 0 means delay is not supported to introduce after chipselect is + * asserted. + * @max_cs_hold_ns: the maximum delay supported before chipselect is deasserted, + * in ns unit, 0 means delay is not supported to introduce before chipselect + * is deasserted. + * @max_cs_incative_ns: maximum delay supported after chipselect is deasserted, + * in ns unit, 0 means delay is not supported to introduce after chipselect is + * deasserted. + */ +struct virtio_spi_config { + /* # of /dev/spidev.CS with CS=0..chip_select_max_number -1 */ + __u8 cs_max_number; + __u8 cs_change_supported; +#define VIRTIO_SPI_RX_TX_SUPPORT_DUAL (1 << 0) +#define VIRTIO_SPI_RX_TX_SUPPORT_QUAD (1 << 1) +#define VIRTIO_SPI_RX_TX_SUPPORT_OCTAL (1 << 2) + __u8 tx_nbits_supported; + __u8 rx_nbits_supported; + __le32 bits_per_word_mask; +#define VIRTIO_SPI_MF_SUPPORT_CPHA_0 (1 << 0) +#define VIRTIO_SPI_MF_SUPPORT_CPHA_1 (1 << 1) +#define VIRTIO_SPI_MF_SUPPORT_CPOL_0 (1 << 2) +#define VIRTIO_SPI_MF_SUPPORT_CPOL_1 (1 << 3) +#define VIRTIO_SPI_MF_SUPPORT_CS_HIGH (1 << 4) +#define VIRTIO_SPI_MF_SUPPORT_LSB_FIRST (1 << 5) +#define VIRTIO_SPI_MF_SUPPORT_LOOPBACK (1 << 6) + __le32 mode_func_supported; + __le32 max_freq_hz; + __le32 max_word_delay_ns; + __le32 max_cs_setup_ns; + __le32 max_cs_hold_ns; + __le32 max_cs_inactive_ns; +}; + +/* + * @chip_select_id: chipselect index the SPI transfer used. + * + * @bits_per_word: the number of bits in each SPI transfer word. + * + * @cs_change: whether to deselect device after finishing this transfer + * before starting the next transfer, 0 means cs keep asserted and + * 1 means cs deasserted then asserted again. + * + * @tx_nbits: bus width for write transfer. + * 0,1: bus width is 1, also known as SINGLE + * 2 : bus width is 2, also known as DUAL + * 4 : bus width is 4, also known as QUAD + * 8 : bus width is 8, also known as OCTAL + * other values are invalid. + * + * @rx_nbits: bus width for read transfer. + * 0,1: bus width is 1, also known as SINGLE + * 2 : bus width is 2, also known as DUAL + * 4 : bus width is 4, also known as QUAD + * 8 : bus width is 8, also known as OCTAL + * other values are invalid. + * + * @reserved: for future use. + * + * @mode: SPI transfer mode. + * bit 0: CPHA, determines the timing (i.e. phase) of the data + * bits relative to the clock pulses.For CPHA=0, the + * "out" side changes the data on the trailing edge of the + * preceding clock cycle, while the "in" side captures the data + * on (or shortly after) the leading edge of the clock cycle. + * For CPHA=1, the "out" side changes the data on the leading + * edge of the current clock cycle, while the "in" side + * captures the data on (or shortly after) the trailing edge of + * the clock cycle. + * bit 1: CPOL, determines the polarity of the clock. CPOL=0 is a + * clock which idles at 0, and each cycle consists of a pulse + * of 1. CPOL=1 is a clock which idles at 1, and each cycle + * consists of a pulse of 0. + * bit 2: CS_HIGH, if 1, chip select active high, else active low. + * bit 3: LSB_FIRST, determines per-word bits-on-wire, if 0, MSB + * first, else LSB first. + * bit 4: LOOP, loopback mode. + * + * @freq: the transfer speed in Hz. + * + * @word_delay_ns: delay to be inserted between consecutive words of a + * transfer, in ns unit. + * + * @cs_setup_ns: delay to be introduced after CS is asserted, in ns + * unit. + * + * @cs_delay_hold_ns: delay to be introduced before CS is deasserted + * for each transfer, in ns unit. + * + * @cs_change_delay_inactive_ns: delay to be introduced after CS is + * deasserted and before next asserted, in ns unit. + */ +struct spi_transfer_head { + __u8 chip_select_id; + __u8 bits_per_word; + __u8 cs_change; + __u8 tx_nbits; + __u8 rx_nbits; + __u8 reserved[3]; + __le32 mode; + __le32 freq; + __le32 word_delay_ns; + __le32 cs_setup_ns; + __le32 cs_delay_hold_ns; + __le32 cs_change_delay_inactive_ns; +}; + +struct spi_transfer_result { +#define VIRTIO_SPI_TRANS_OK 0 +#define VIRTIO_SPI_PARAM_ERR 1 +#define VIRTIO_SPI_TRANS_ERR 2 + u8 result; +}; + +#endif /* #ifndef _LINUX_VIRTIO_VIRTIO_SPI_H */