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Mon, 10 Apr 2023 18:46:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT085.mail.protection.outlook.com (10.13.172.236) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6298.26 via Frontend Transport; Mon, 10 Apr 2023 18:46:25 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 10 Apr 2023 13:46:21 -0500 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v13 04/15] dt-bindings: spi: dw: Add AMD Pensando Elba SoC SPI Controller Date: Mon, 10 Apr 2023 11:45:15 -0700 Message-ID: <20230410184526.15990-5-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230410184526.15990-1-blarson@amd.com> References: <20230410184526.15990-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT085:EE_|SA3PR12MB7923:EE_ X-MS-Office365-Filtering-Correlation-Id: 95cacab3-1af3-4645-21d1-08db39f3e31f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 18:46:25.2736 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95cacab3-1af3-4645-21d1-08db39f3e31f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT085.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7923 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The AMD Pensando Elba SoC has integrated the DW APB SPI Controller Signed-off-by: Brad Larson Reviewed-by: Krzysztof Kozlowski Reviewed-by: Serge Semin --- v12 changes: - Correct property amd,pensando-elba-syscon description v10 changes: - Move definition of amd,pensando-elba-syscon into properties with a better description - Add amd,pensando-elba-syscon: false for non elba designs v9 changes: - Define property amd,pensando-elba-syscon - Move compatible amd,pensando-elba-spi ahead of baikal,bt1-ssi --- .../bindings/spi/snps,dw-apb-ssi.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index a132b5fc56e0..12ca108864c6 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -37,6 +37,17 @@ allOf: else: required: - interrupts + - if: + properties: + compatible: + contains: + const: amd,pensando-elba-spi + then: + required: + - amd,pensando-elba-syscon + else: + properties: + amd,pensando-elba-syscon: false properties: compatible: @@ -63,6 +74,8 @@ properties: const: intel,keembay-ssi - description: Intel Thunder Bay SPI Controller const: intel,thunderbay-ssi + - description: AMD Pensando Elba SoC SPI Controller + const: amd,pensando-elba-spi - description: Baikal-T1 SPI Controller const: baikal,bt1-ssi - description: Baikal-T1 System Boot SPI Controller @@ -136,6 +149,12 @@ properties: of the designware controller, and the upper limit is also subject to controller configuration. + amd,pensando-elba-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Block address to control SPI chip-selects. The Elba SoC system controller + provides an interface to override the native DWC SSI CS control. + patternProperties: "^.*@[0-9a-f]+$": type: object