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Mon, 20 Mar 2023 05:03:11 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 20 Mar 2023 05:03:09 -0500 From: Sai Krishna Potthuri To: Mark Brown CC: , , , , Sai Krishna Potthuri Subject: [PATCH 2/2] spi: cadence-quadspi: Disable the SPI before reconfiguring Date: Mon, 20 Mar 2023 15:29:31 +0530 Message-ID: <20230320095931.2651714-3-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> References: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT078:EE_|SJ0PR12MB5405:EE_ X-MS-Office365-Filtering-Correlation-Id: c77c9134-e28f-4ffe-3565-08db292a5b82 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Idvdal2HXUPChA0MkqvVO9I/PDLqMIykY93cO9dyR8o13XoYPtqDq1fV/eQrLHjspvu2bqNHAI/euMqg9oVvBY2jtce9LuvwEEcwjvP70p8ZVtIpLlsNgzYR86M7+ifwx7DlUoPH6FKaS86y1BriLGzWFVnUYtIVaNLsFAKCgvHicZ5i2v2if2wOV97b6xziTQAc89AV2Z3jXhui8uodFE1RlbvjEoBqJRjlS+ZwtVIhGjzlHuySPoZKR0gJFjC9vaqPsz4auujnw5guZzUuHag64YERulZdk9v9tc7Bb0wflJ1fIsED/Sw1PdCKXNbI24qtTakXWwQpT75oGlLuuH4Ba9zkWfBoEZbVTWVqPcZgn2kiwxnNpPXhwh4oqGbITX9ohe+U2g0Mf5wz3ln/9Q7bLd5lhiSMVRW9UkVKeBY2CH4xYCQQ+ust2bH2soA6rpylcJVDPZLRFIpUlCBfF/2D1hTLhPnmrRjQNCSlTV0dzP4azmwyOWM+D7Lf3O6v1duOWOj+YeAp20RxB9ZfoBE1Gvj5UUbiGBY50II01JxZGxkja7XBYwRat6OZKEu963Sc+dXxsPLta5EBLurXDViU3lv/bSNpvgSAjlgZidpO+sMnrsHK5Sv4494HnkMayBedNIb8igu4zfBsFRKm7AlCTZreNMfxQW8/Tpt0Ut7TDgralrntGIrGaD0PA4st0Bkg0DMxjQdrtJCSq9QPRFITmNWC60haHGMi5iCRm6k= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(396003)(346002)(376002)(136003)(39860400002)(451199018)(36840700001)(46966006)(40470700004)(2616005)(426003)(47076005)(478600001)(83380400001)(6666004)(336012)(316002)(8676002)(70206006)(6916009)(70586007)(186003)(26005)(1076003)(54906003)(4326008)(36860700001)(41300700001)(5660300002)(8936002)(40460700003)(81166007)(82740400003)(2906002)(356005)(40480700001)(82310400005)(86362001)(36756003)(103116003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2023 10:03:30.1963 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c77c9134-e28f-4ffe-3565-08db292a5b82 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5405 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Observed random DMA timeout failures while doing back to back transfers which involves switching the modes from DMA to NON-DMA. This issue is observed while testing the OSPI+UBIFS file system test case where rootfs is mounted from OSPI UBIFS partition. To avoid this issue, disable the SPI before changing the configuration from external DMA to NON-DMA and vice versa and reenable it after changing the configuration. As per the Cadence Octal SPI design specification, it is recommended to disable the Octal-SPI enable bit before reconfiguring. Signed-off-by: Sai Krishna Potthuri --- drivers/spi/spi-cadence-quadspi.c | 38 +++++++++++++++++++------------ 1 file changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index e281732aba91..d4a2b72985da 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -791,6 +791,21 @@ static int cqspi_indirect_read_execute(struct cqspi_flash_pdata *f_pdata, return ret; } +static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) +{ + void __iomem *reg_base = cqspi->iobase; + unsigned int reg; + + reg = readl(reg_base + CQSPI_REG_CONFIG); + + if (enable) + reg |= CQSPI_REG_CONFIG_ENABLE_MASK; + else + reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; + + writel(reg, reg_base + CQSPI_REG_CONFIG); +} + static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, u_char *rxbuf, loff_t from_addr, size_t n_rx) @@ -815,10 +830,14 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, if (ret) return ret; + cqspi_controller_enable(cqspi, 0); + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); reg |= CQSPI_REG_CONFIG_DMA_MASK; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + cqspi_controller_enable(cqspi, 1); + dma_addr = dma_map_single(dev, rxbuf, bytes_to_dma, DMA_FROM_DEVICE); if (dma_mapping_error(dev, dma_addr)) { dev_err(dev, "dma mapping failed\n"); @@ -876,10 +895,14 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, cqspi->iobase + CQSPI_REG_INDIRECTRD); dma_unmap_single(dev, dma_addr, bytes_to_dma, DMA_FROM_DEVICE); + cqspi_controller_enable(cqspi, 0); + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); reg &= ~CQSPI_REG_CONFIG_DMA_MASK; writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); + cqspi_controller_enable(cqspi, 1); + ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); if (ret) @@ -1182,21 +1205,6 @@ static void cqspi_readdata_capture(struct cqspi_st *cqspi, writel(reg, reg_base + CQSPI_REG_READCAPTURE); } -static void cqspi_controller_enable(struct cqspi_st *cqspi, bool enable) -{ - void __iomem *reg_base = cqspi->iobase; - unsigned int reg; - - reg = readl(reg_base + CQSPI_REG_CONFIG); - - if (enable) - reg |= CQSPI_REG_CONFIG_ENABLE_MASK; - else - reg &= ~CQSPI_REG_CONFIG_ENABLE_MASK; - - writel(reg, reg_base + CQSPI_REG_CONFIG); -} - static void cqspi_configure(struct cqspi_flash_pdata *f_pdata, unsigned long sclk) {