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Mon, 20 Mar 2023 05:03:09 -0500 Received: from xhdlakshmis40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 20 Mar 2023 05:03:07 -0500 From: Sai Krishna Potthuri To: Mark Brown CC: , , , , Sai Krishna Potthuri Subject: [PATCH 1/2] spi: cadence-quadspi: Update the read timeout based on the length Date: Mon, 20 Mar 2023 15:29:30 +0530 Message-ID: <20230320095931.2651714-2-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> References: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1NAM11FT056:EE_|PH7PR12MB6465:EE_ X-MS-Office365-Filtering-Correlation-Id: 7e81110b-f3b0-4bca-f6ea-08db292a5aa0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 27hyF+Dwq2ElV7AvQe0Oj2jxXC7VwgpPTuzELYv7D8iP8iaiK2rzm8WB3/zrhXhXMRo2N+mMGBr3J7bZcR5KPWSo8gosyUhGcjvZAjfHsX26Z85KhAlw/PYXtG+NabcHZLh/nJ1GS/eDTH0fkp4LPEMSRixhP7dXAbdKjhzEirkQ8P35K2S2//95E+/8inXJYni6/7f0XcRHzIBrzRB042CtQVpps3+c8pXzO5yc4KPyzY2UPwq1iVy4nhZZuNtUw8uRZjSkJnsQYgBtmftNk/mMBgiZ1/mQHWwM2pS4n9m5sWZ0QrXTmvniYW6zeBl+Qlfq65uH25s5ACRrYsbXzljflfo6gFxXp7s9GsH4+jiJTPUtRjNwCUhYyTm6NpJVAG+JM0+yqfYnwWoJfxsRMNcKdbCYN+M6LglJ9iLR0SQIA276haXrZgchQw0e73+hT8GEXwssgQsh1Ipvq1hUvNRGe/8mUlbdMZ6o8oRw03L5IvgkTR4RJ4qLmbwBPvtETWtPN7s1DxQAKldnhl2hJoZTr5mUXl1aFZuVSNv/+YM1LcfUy0wRPgrYWRBeC8Xhtvgo4VCZMSgfCxbM+ZPRMTy1LlRKGMfztEOOJlieE4H1+dCvOzBdC1BiTB/K8F+AUY4hYWQCiwp+lCenzpUwTXI5uFsTV7PKtfXpj9cbEzO90NeC2tkHnS5wpbzGcVoS0j/HKpunkfLCsKM0tdyc2BeONyZPHfmyeKTPLXFedyo= X-Forefront-Antispam-Report: CIP:165.204.84.17; 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For reads larger than 500 bytes, the timeout will continue to be equal to the read length whereas for a small read like the Read Status Register command, the timeout would be 1 or 2 milliseconds. This is not enough to cover the overhead needed in setting up DMA, in that case make sure the timeout is at least 500ms to allow DMA to finish. This solution is inline with the timeout used for Direct read via DMA. Signed-off-by: Sai Krishna Potthuri --- drivers/spi/spi-cadence-quadspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 79ab7e309644..e281732aba91 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -863,7 +863,7 @@ static int cqspi_versal_indirect_read_dma(struct cqspi_flash_pdata *f_pdata, reinit_completion(&cqspi->transfer_complete); if (!wait_for_completion_timeout(&cqspi->transfer_complete, - msecs_to_jiffies(CQSPI_READ_TIMEOUT_MS))) { + msecs_to_jiffies(max_t(size_t, bytes_to_dma, 500)))) { ret = -ETIMEDOUT; goto failrd; }