From patchwork Sun Mar 12 00:44:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Brad Larson X-Patchwork-Id: 662645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F237C61DA4 for ; Sun, 12 Mar 2023 00:47:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229656AbjCLArA (ORCPT ); Sat, 11 Mar 2023 19:47:00 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229756AbjCLAq7 (ORCPT ); Sat, 11 Mar 2023 19:46:59 -0500 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2080.outbound.protection.outlook.com [40.107.220.80]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ED663CE02; Sat, 11 Mar 2023 16:46:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Z2GjgjUmi2d28RSGFhuY37fMS/RwG9XooO7wDbN5CmFv0Qxc7MjgMj3PcknRtHZvwuVYH6EgeCasugcOksQVizkIG60KRS8zVOJVkKc/PtvFVi/bh4qrq7vC5xesncVJY97tiQIIJ9pGgo/ZzxbllkOsNPrvcLMbJDSOYrhSMlg9Lkg/rjQnbuvtXETAQzajGvtMXfhf1N+pzC5s0ztVBDe13ytfQHXpD3XEK4yk1bW1YhLqyDAexX3VJuT2Kk2oViJunjL6HVTO8KpvmMz5UNO6GVp6mgy8inSMID7qF8O9mkqs6Fhoj51YPenIFOHGWeGiWWOFWp42eiepwYA14A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=j7imN6SgaVAurHho6Pd+K0ALCxGZP41vTmEWNf+XI7s=; b=M6K73/z7mbQoa5EH24ZKgkfF2PyiQvcel9kYVvU2Lzg3uU+56B+ROIaAgvGL8Pn9hiMor8UKXPbCosP9ad8zjHzKAk/+1IkZG7yvrOLAEG0+eHSzVb2QjgaSHmytqa+ZWGIluz5Qp/uY5abxeKWVV7mKSsK731rR/V2cXO2fi09h1FCy3HTcPzVqdtsyzKbZQQRFJoNsUuAzCzKZYiVZtIDWx7nbLOFmZheZH+aWt44/gekk9856P6+Pw4gkdv+LEaA5O3SYHj6vJeVX1n73bc+3qNoVYfuqWl+0pA8JcfNxSzP6i0Hrclgd/dY2R4XEHWSG5qw+K67AVUKFgdRH1w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=lists.infradead.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=j7imN6SgaVAurHho6Pd+K0ALCxGZP41vTmEWNf+XI7s=; b=38/TcUL9nxgD1rNYJo1qY2Fq4iUEbgPWmeEvLQfDTfS1zOxLlhGqHzxTc7MV8kwcgoZy6qbXAEzQAFRzbqRk0OoMkhlzydt7vQBT9+G6tPgF4mNr4dtPefyeDgS2KyMzzeBdp+i2obPOC1JWc0QYaBMRK8VwlKRZFkb8041gZ84= Received: from DM6PR13CA0046.namprd13.prod.outlook.com (2603:10b6:5:134::23) by IA1PR12MB8261.namprd12.prod.outlook.com (2603:10b6:208:3f7::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.23; Sun, 12 Mar 2023 00:46:09 +0000 Received: from DM6NAM11FT029.eop-nam11.prod.protection.outlook.com (2603:10b6:5:134:cafe::e5) by DM6PR13CA0046.outlook.office365.com (2603:10b6:5:134::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6178.24 via Frontend Transport; Sun, 12 Mar 2023 00:46:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT029.mail.protection.outlook.com (10.13.173.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.22 via Frontend Transport; Sun, 12 Mar 2023 00:46:08 +0000 Received: from platform-dev1.pensando.io (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Sat, 11 Mar 2023 18:46:05 -0600 From: Brad Larson To: CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v11 08/15] arm64: dts: Add AMD Pensando Elba SoC support Date: Sat, 11 Mar 2023 16:44:38 -0800 Message-ID: <20230312004445.15913-9-blarson@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230312004445.15913-1-blarson@amd.com> References: <20230312004445.15913-1-blarson@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT029:EE_|IA1PR12MB8261:EE_ X-MS-Office365-Filtering-Correlation-Id: c08f16d6-b926-4acc-551a-08db22932b8f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: jB05pc4FV/xEGJ+0UnXRY9lU9x39AHnv7k/lflQAOQ9tOQrzxQzYLIUcvSGwlOmmUj8+0F1R8N5f6/zCFM/n9P6R7Ow051TeI1t5vC+jg5qQRd8api78EUmxG4eRQI2qy9PdlCUXN4g3LL6VhelohC3zqksz1YJobQYJhZvp5kkhUdAgjUyq00z6+PAhGRB6d3r5vdrpSQA766RX3wpiIiJpGVNJlR7DY3JYdX5gdlGQzyB6WCNRyGioPsTbjnVLrVoUCRNmFb7R9SlU/8Mz79LKJ+CQfQrRir3GD+yBUsXGN0BB54uzjl1jPH7I5/yFFdwPY4KC86XgxLnS3v058U8h1SCHxzT2fc2QXamQcwhiA0qaLK9WSS/WQ3m9IQdpnn6QX9CCCP5jIRPuZ0D/EQj6i3E8GbNBza4FBif3ARtt/9kuAS7cPB3kCf1H/4k9IqIgi1266qIZ68JIFRX2gNIoFjq6XVCndpD8c90Ov28uS9ph+iqTL7wJ/B4pBJSg/29yHQitwWUp2UwVHYn1wlv1WTzlV0MLSyZ2d6pfS1Wz5dG77bJIKCm6LN3Wi0mL9vxZyLcxS1bO3chzURz6eUgcuuCdFwXd9vU1hi/PCQGkK2iZ1sN29f5QmZP6mjW9nD1U1zApRO+BR4qbw5Hsmi+h7w1+nuWft5Vs3dVvtLzxd6JMBG+XYR9/0ai/qh9zHQuRFSk7nmNHNQaeYNuH3xyWVMPBv1YCXT4HmaZ17eM= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(346002)(39860400002)(396003)(136003)(376002)(451199018)(40470700004)(46966006)(36840700001)(336012)(2616005)(16526019)(7416002)(7406005)(186003)(30864003)(1076003)(26005)(83380400001)(8936002)(6666004)(82310400005)(36860700001)(356005)(82740400003)(81166007)(5660300002)(426003)(47076005)(40480700001)(8676002)(40460700003)(4326008)(70586007)(2906002)(6916009)(70206006)(41300700001)(478600001)(316002)(36756003)(54906003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Mar 2023 00:46:08.8626 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c08f16d6-b926-4acc-551a-08db22932b8f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT029.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8261 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Add AMD Pensando common and Elba SoC specific device nodes Signed-off-by: Brad Larson --- v11 changes: - Delete reset-names - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl' v9 changes: - Single node for spi0 system-controller and squash the reset-controller child into parent --- arch/arm64/boot/dts/amd/Makefile | 1 + arch/arm64/boot/dts/amd/elba-16core.dtsi | 189 +++++++++++++++++ arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 ++++++++ arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++ arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++ arch/arm64/boot/dts/amd/elba.dtsi | 192 ++++++++++++++++++ 6 files changed, 596 insertions(+) create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile index 68103a8b0ef5..8502cc2afbc5 100644 --- a/arch/arm64/boot/dts/amd/Makefile +++ b/arch/arm64/boot/dts/amd/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi new file mode 100644 index 000000000000..37aadd442db8 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi @@ -0,0 +1,189 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/ { + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { cpu = <&cpu0>; }; + core1 { cpu = <&cpu1>; }; + core2 { cpu = <&cpu2>; }; + core3 { cpu = <&cpu3>; }; + }; + + cluster1 { + core0 { cpu = <&cpu4>; }; + core1 { cpu = <&cpu5>; }; + core2 { cpu = <&cpu6>; }; + core3 { cpu = <&cpu7>; }; + }; + + cluster2 { + core0 { cpu = <&cpu8>; }; + core1 { cpu = <&cpu9>; }; + core2 { cpu = <&cpu10>; }; + core3 { cpu = <&cpu11>; }; + }; + + cluster3 { + core0 { cpu = <&cpu12>; }; + core1 { cpu = <&cpu13>; }; + core2 { cpu = <&cpu14>; }; + core3 { cpu = <&cpu15>; }; + }; + }; + + /* CLUSTER 0 */ + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x0>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x1>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x2>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x3>; + next-level-cache = <&l2_0>; + enable-method = "psci"; + }; + + l2_0: l2-cache0 { + compatible = "cache"; + }; + + /* CLUSTER 1 */ + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x100>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x101>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x102>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x103>; + next-level-cache = <&l2_1>; + enable-method = "psci"; + }; + + l2_1: l2-cache1 { + compatible = "cache"; + }; + + /* CLUSTER 2 */ + cpu8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x200>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x201>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x202>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + cpu11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x203>; + next-level-cache = <&l2_2>; + enable-method = "psci"; + }; + + l2_2: l2-cache2 { + compatible = "cache"; + }; + + /* CLUSTER 3 */ + cpu12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x300>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x301>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x302>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + cpu15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0 0x303>; + next-level-cache = <&l2_3>; + enable-method = "psci"; + }; + + l2_3: l2-cache3 { + compatible = "cache"; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi new file mode 100644 index 000000000000..1a615788f54e --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&ahb_clk { + clock-frequency = <400000000>; +}; + +&emmc_clk { + clock-frequency = <200000000>; +}; + +&flash_clk { + clock-frequency = <400000000>; +}; + +&ref_clk { + clock-frequency = <156250000>; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-rx-bus-width = <2>; + m25p,fast-read; + cdns,read-delay = <0>; + cdns,tshsl-ns = <0>; + cdns,tsd2d-ns = <0>; + cdns,tchsh-ns = <0>; + cdns,tslch-ns = <0>; + }; +}; + +&gpio0 { + status = "okay"; +}; + +&emmc { + bus-width = <8>; + cap-mmc-hw-reset; + resets = <&rstc 0>; + status = "okay"; +}; + +&wdt0 { + status = "okay"; +}; + +&i2c0 { + clock-frequency = <100000>; + status = "okay"; + + rtc@51 { + compatible = "nxp,pcf85263"; + reg = <0x51>; + }; +}; + +&spi0 { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, + <&porta 7 GPIO_ACTIVE_LOW>; + status = "okay"; + + rstc: system-controller@0 { + compatible = "amd,pensando-elba-ctrl"; + reg = <0>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts new file mode 100644 index 000000000000..c3f4da2f7449 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-asic.dts @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Device Tree file for AMD Pensando Elba Board. + * + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +/dts-v1/; + +#include "elba.dtsi" +#include "elba-16core.dtsi" +#include "elba-asic-common.dtsi" +#include "elba-flash-parts.dtsi" + +/ { + model = "AMD Pensando Elba Board"; + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba"; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + spi1 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi new file mode 100644 index 000000000000..734893fef2c3 --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +&flash0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "flash"; + reg = <0x10000 0xfff0000>; + }; + + partition@f0000 { + label = "golduenv"; + reg = <0xf0000 0x10000>; + }; + + partition@100000 { + label = "boot0"; + reg = <0x100000 0x80000>; + }; + + partition@180000 { + label = "golduboot"; + reg = <0x180000 0x200000>; + }; + + partition@380000 { + label = "brdcfg0"; + reg = <0x380000 0x10000>; + }; + + partition@390000 { + label = "brdcfg1"; + reg = <0x390000 0x10000>; + }; + + partition@400000 { + label = "goldfw"; + reg = <0x400000 0x3c00000>; + }; + + partition@4010000 { + label = "fwmap"; + reg = <0x4010000 0x20000>; + }; + + partition@4030000 { + label = "fwsel"; + reg = <0x4030000 0x20000>; + }; + + partition@4090000 { + label = "bootlog"; + reg = <0x4090000 0x20000>; + }; + + partition@40b0000 { + label = "panicbuf"; + reg = <0x40b0000 0x20000>; + }; + + partition@40d0000 { + label = "uservars"; + reg = <0x40d0000 0x20000>; + }; + + partition@4200000 { + label = "uboota"; + reg = <0x4200000 0x400000>; + }; + + partition@4600000 { + label = "ubootb"; + reg = <0x4600000 0x400000>; + }; + + partition@4a00000 { + label = "mainfwa"; + reg = <0x4a00000 0x1000000>; + }; + + partition@5a00000 { + label = "mainfwb"; + reg = <0x5a00000 0x1000000>; + }; + + partition@6a00000 { + label = "diaguboot"; + reg = <0x6a00000 0x400000>; + }; + + partition@8000000 { + label = "diagfw"; + reg = <0x8000000 0x7fe0000>; + }; + + partition@ffe0000 { + label = "ubootenv"; + reg = <0xffe0000 0x10000>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/amd/elba.dtsi b/arch/arm64/boot/dts/amd/elba.dtsi new file mode 100644 index 000000000000..285d776aa67b --- /dev/null +++ b/arch/arm64/boot/dts/amd/elba.dtsi @@ -0,0 +1,192 @@ +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +/* + * Copyright 2020-2022 Advanced Micro Devices, Inc. + */ + +#include +#include "dt-bindings/interrupt-controller/arm-gic.h" + +/ { + model = "Elba ASIC Board"; + compatible = "amd,pensando-elba"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + dma-coherent; + + ahb_clk: oscillator0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + emmc_clk: oscillator2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + flash_clk: oscillator3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + ref_clk: oscillator4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = ; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + i2c0: i2c@400 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x400 0x0 0x100>; + clocks = <&ahb_clk>; + #address-cells = <1>; + #size-cells = <0>; + i2c-sda-hold-time-ns = <480>; + snps,sda-timeout-ms = <750>; + interrupts = ; + status = "disabled"; + }; + + wdt0: watchdog@1400 { + compatible = "snps,dw-wdt"; + reg = <0x0 0x1400 0x0 0x100>; + clocks = <&ahb_clk>; + interrupts = ; + status = "disabled"; + }; + + qspi: spi@2400 { + compatible = "amd,pensando-elba-qspi", "cdns,qspi-nor"; + reg = <0x0 0x2400 0x0 0x400>, + <0x0 0x7fff0000 0x0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&flash_clk>; + cdns,fifo-depth = <1024>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x7fff0000>; + status = "disabled"; + }; + + spi0: spi@2800 { + compatible = "amd,pensando-elba-spi"; + reg = <0x0 0x2800 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + amd,pensando-elba-syscon = <&syscon>; + clocks = <&ahb_clk>; + interrupts = ; + num-cs = <2>; + status = "disabled"; + }; + + gpio0: gpio@4000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x0 0x4000 0x0 0x78>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + reg = <0>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + interrupts = ; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + reg = <1>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <8>; + }; + }; + + uart0: serial@4800 { + compatible = "ns16550a"; + reg = <0x0 0x4800 0x0 0x100>; + clocks = <&ref_clk>; + interrupts = ; + reg-shift = <2>; + reg-io-width = <4>; + }; + + gic: interrupt-controller@800000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x800000 0x0 0x200000>, /* GICD */ + <0x0 0xa00000 0x0 0x200000>, /* GICR */ + <0x0 0x60000000 0x0 0x2000>, /* GICC */ + <0x0 0x60010000 0x0 0x1000>, /* GICH */ + <0x0 0x60020000 0x0 0x2000>; /* GICV */ + #address-cells = <2>; + #size-cells = <2>; + #interrupt-cells = <3>; + ranges; + interrupt-controller; + interrupts = ; + + /* + * Elba specific pre-ITS is enabled using the + * existing property socionext,synquacer-pre-its + */ + gic_its: msi-controller@820000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x820000 0x0 0x10000>; + msi-controller; + #msi-cells = <1>; + socionext,synquacer-pre-its = + <0xc00000 0x1000000>; + }; + }; + + emmc: mmc@30440000 { + compatible = "amd,pensando-elba-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x30440000 0x0 0x10000>, + <0x0 0x30480044 0x0 0x4>; /* byte-lane ctrl */ + clocks = <&emmc_clk>; + interrupts = ; + cdns,phy-input-delay-sd-highspeed = <0x4>; + cdns,phy-input-delay-legacy = <0x4>; + cdns,phy-input-delay-sd-uhs-sdr50 = <0x6>; + cdns,phy-input-delay-sd-uhs-ddr50 = <0x16>; + mmc-ddr-1_8v; + status = "disabled"; + }; + + syscon: syscon@307c0000 { + compatible = "amd,pensando-elba-syscon", "syscon"; + reg = <0x0 0x307c0000 0x0 0x3000>; + }; + }; +};