From patchwork Wed Jan 25 08:10:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dhruva Gole X-Patchwork-Id: 647007 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3041C54E94 for ; Wed, 25 Jan 2023 08:11:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234961AbjAYILX (ORCPT ); Wed, 25 Jan 2023 03:11:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233330AbjAYILQ (ORCPT ); Wed, 25 Jan 2023 03:11:16 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A0A6F4709D; Wed, 25 Jan 2023 00:11:13 -0800 (PST) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 30P8B4vn059195; Wed, 25 Jan 2023 02:11:04 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1674634264; bh=H6KisuMO1+dkW1oxul0NcexVOnMzVPplM1t3KZiQg1k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=kOFvGhQcoiLPwPe7UJSzl0nr8TqRqydgJB/MPGsi9jteq/L4Wc0GpUnGoBI+XQ/l9 vhI3wub9h+aksqOoUbO+uT+BCGQFXvlHAcXGs5hq8mrRZrIoxynmt5u6c9mu9bcX7I 7vkG7DIUOyp7eSrVFA4fz1E8TjExPh6vR0tNI6T0= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 30P8B4Op027318 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Jan 2023 02:11:04 -0600 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 25 Jan 2023 02:11:04 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 25 Jan 2023 02:11:04 -0600 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 30P8B2mg075654; Wed, 25 Jan 2023 02:11:03 -0600 From: Dhruva Gole To: Mark Brown CC: , , Vignesh Raghavendra , Vaishnav Achath , Dhruva Gole , , , , Pratyush Yadav Subject: [PATCH v2 3/4] spi: cadence-quadspi: setup ADDR Bits in cmd reads Date: Wed, 25 Jan 2023 13:40:22 +0530 Message-ID: <20230125081023.1573712-4-d-gole@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230125081023.1573712-1-d-gole@ti.com> References: <20230125081023.1573712-1-d-gole@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Setup the Addr bit field while issuing register reads in STIG mode. This is needed for example flashes like cypress define in their transaction table that to read any register there is 1 cmd byte and a few more address bytes trailing the cmd byte. Absence of addr bytes will obviously fail to read correct data from flash register that maybe requested by flash driver because the controller doesn't even specify which address of the flash register the read is being requested from. Signed-off-by: Dhruva Gole --- drivers/spi/spi-cadence-quadspi.c | 11 +++++++++++ 1 file changed, 11 insertions(+) -- 2.25.1 diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 4bbf6e3ad34a..a6d0f1b0bb49 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -532,6 +532,17 @@ static int cqspi_command_read(struct cqspi_flash_pdata *f_pdata, /* 0 means 1 byte. */ reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) << CQSPI_REG_CMDCTRL_RD_BYTES_LSB); + + /* setup ADDR BIT field */ + if (op->addr.nbytes) { + reg |= (0x1 << CQSPI_REG_CMDCTRL_ADDR_EN_LSB); + reg |= ((op->addr.nbytes - 1) & + CQSPI_REG_CMDCTRL_ADD_BYTES_MASK) + << CQSPI_REG_CMDCTRL_ADD_BYTES_LSB; + + writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); + } + status = cqspi_exec_flash_cmd(cqspi, reg); if (status) return status;