From patchwork Tue Jan 24 22:12:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Zhang X-Patchwork-Id: 647012 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C63AEC54E94 for ; Tue, 24 Jan 2023 22:33:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230410AbjAXWdo (ORCPT ); Tue, 24 Jan 2023 17:33:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233524AbjAXWdf (ORCPT ); Tue, 24 Jan 2023 17:33:35 -0500 Received: from relay.smtp-ext.broadcom.com (lpdvsmtp11.broadcom.com [192.19.166.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5304753558; Tue, 24 Jan 2023 14:33:10 -0800 (PST) Received: from mail-lvn-it-01.lvn.broadcom.net (mail-lvn-it-01.lvn.broadcom.net [10.75.146.107]) by relay.smtp-ext.broadcom.com (Postfix) with ESMTP id 436CAC0000FC; Tue, 24 Jan 2023 14:33:10 -0800 (PST) DKIM-Filter: OpenDKIM Filter v2.11.0 relay.smtp-ext.broadcom.com 436CAC0000FC DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=broadcom.com; s=dkimrelay; t=1674599590; bh=uCIT4WkEwESkcQXbcHTvT/VVmK1L0H4DtPalP4EYkAY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HERIvobJNoEP23NMiuRvOaMiX3m1KuIdgh4WRmES88fsRNU3dWbHVvAighsBgJlqg 6W5/QtPOuX52Y2XLihpIhlGuftYcAXUe4DFZZyKrJ9/GCjKS3DtOL8uhBn+ZobrJSp P2dmMgJXzPjdgGl6/K7hSX4Wfpv/CSz1mzs8Yhn0= Received: from bcacpedev-irv-3.lvn.broadcom.net (bcacpedev-irv-3.lvn.broadcom.net [10.75.138.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail-lvn-it-01.lvn.broadcom.net (Postfix) with ESMTPS id 41DFF18041CAC6; Tue, 24 Jan 2023 14:33:10 -0800 (PST) Received: by bcacpedev-irv-3.lvn.broadcom.net (Postfix, from userid 28376) id 790B1101B56; Tue, 24 Jan 2023 14:33:03 -0800 (PST) From: William Zhang To: Linux SPI List , Broadcom Kernel List Cc: tomer.yacoby@broadcom.com, kursad.oney@broadcom.com, dregan@mail.com, f.fainelli@gmail.com, anand.gore@broadcom.com, jonas.gorski@gmail.com, dan.beygelman@broadcom.com, joel.peshkin@broadcom.com, William Zhang , Mark Brown , linux-kernel@vger.kernel.org Subject: [PATCH v2 09/14] spi: bcm63xx-hsspi: Fix multi-bit mode setting Date: Tue, 24 Jan 2023 14:12:12 -0800 Message-Id: <20230124221218.341511-10-william.zhang@broadcom.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20230124221218.341511-1-william.zhang@broadcom.com> References: <20230124221218.341511-1-william.zhang@broadcom.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Currently the driver always sets the controller to dual data bit mode for both tx and rx data in the profile mode control register even for single data bit transfer. Luckily the opcode is set correctly according to SPI transfer data bit width so it does not actually cause issues. This change fixes the problem by setting tx and rx data bit mode field correctly according to the actual SPI transfer tx and rx data bit width. Fixes: 142168eba9dc ("spi: bcm63xx-hsspi: add bcm63xx HSSPI driver") Signed-off-by: William Zhang --- (no changes since v1) drivers/spi/spi-bcm63xx-hsspi.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-bcm63xx-hsspi.c b/drivers/spi/spi-bcm63xx-hsspi.c index 696e14abba2d..8f0d31764f98 100644 --- a/drivers/spi/spi-bcm63xx-hsspi.c +++ b/drivers/spi/spi-bcm63xx-hsspi.c @@ -215,7 +215,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) int step_size = HSSPI_BUFFER_LEN; const u8 *tx = t->tx_buf; u8 *rx = t->rx_buf; - u32 val; + u32 val = 0; unsigned long limit; bcm63xx_hsspi_set_clk(bs, spi, t->speed_hz); @@ -232,11 +232,16 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t) step_size -= HSSPI_OPCODE_LEN; if ((opcode == HSSPI_OP_READ && t->rx_nbits == SPI_NBITS_DUAL) || - (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) + (opcode == HSSPI_OP_WRITE && t->tx_nbits == SPI_NBITS_DUAL)) { opcode |= HSSPI_OP_MULTIBIT; - __raw_writel(1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT | - 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT | 0xff, + if (t->rx_nbits == SPI_NBITS_DUAL) + val |= 1 << MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT; + if (t->tx_nbits == SPI_NBITS_DUAL) + val |= 1 << MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT; + } + + __raw_writel(val | 0xff, bs->regs + HSSPI_PROFILE_MODE_CTRL_REG(chip_select)); while (pending > 0) {