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[78.150.37.98]) by smtp.gmail.com with ESMTPSA id t123-20020a1c4681000000b003a3170a7af9sm10156808wma.4.2022.12.12.10.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Dec 2022 10:07:46 -0800 (PST) From: Sudip Mukherjee To: Serge Semin , Mark Brown , Rob Herring , Krzysztof Kozlowski Cc: jude.onyenegecha@sifive.com, ben.dooks@sifive.com, jeegar.lakhani@sifive.com, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Sudip Mukherjee Subject: [PATCH v2 06/15] spi: dw: Introduce dual/quad/octal spi Date: Mon, 12 Dec 2022 18:07:23 +0000 Message-Id: <20221212180732.79167-7-sudip.mukherjee@sifive.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221212180732.79167-1-sudip.mukherjee@sifive.com> References: <20221212180732.79167-1-sudip.mukherjee@sifive.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org If the spi transfer is using dual/quad/octal spi mode, then we need to update the SPI_CTRLR0 register. The SPI_CTRLR0 register will be updated in dw_spi_update_config() via the values in dw_spi_cfg. Signed-off-by: Sudip Mukherjee --- Note: DW_SPI_SPI_CTRLR0_INST_L_INST_L16 will not work yet as spi_mem_default_supports_op() checks for op->cmd.nbytes != 1. drivers/spi/spi-dw-core.c | 46 +++++++++++++++++++++++++++++++++++++++ drivers/spi/spi-dw.h | 9 ++++++++ 2 files changed, 55 insertions(+) diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c index 89438ae2df17d..06169aa3f37bf 100644 --- a/drivers/spi/spi-dw-core.c +++ b/drivers/spi/spi-dw-core.c @@ -836,10 +836,56 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op * { struct spi_controller *ctlr = mem->spi->controller; struct dw_spi *dws = spi_controller_get_devdata(ctlr); + struct dw_spi_cfg cfg; + + switch (op->data.buswidth) { + case 2: + cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI; + break; + case 4: + cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI; + break; + case 8: + cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_OCT_SPI; + break; + default: + return dw_spi_exec_mem_op(mem, op); + } /* Collect cmd and addr into a single buffer */ dw_spi_init_enh_mem_buf(dws, op); + cfg.dfs = 8; + cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq); + cfg.ndf = op->data.nbytes; + if (op->data.dir == SPI_MEM_DATA_IN) + cfg.tmode = DW_SPI_CTRLR0_TMOD_RO; + else + cfg.tmode = DW_SPI_CTRLR0_TMOD_TO; + if (op->data.buswidth == op->addr.buswidth && + op->data.buswidth == op->cmd.buswidth) + cfg.trans_t = DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT2; + else if (op->data.buswidth == op->addr.buswidth) + cfg.trans_t = DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT1; + else + cfg.trans_t = DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT0; + + cfg.addr_l = clamp(op->addr.nbytes * 2, 0, 0xf); + if (op->cmd.nbytes > 1) + cfg.inst_l = DW_SPI_SPI_CTRLR0_INST_L_INST_L16; + else if (op->cmd.nbytes == 1) + cfg.inst_l = DW_SPI_SPI_CTRLR0_INST_L_INST_L8; + else + cfg.inst_l = DW_SPI_SPI_CTRLR0_INST_L_INST_L0; + + cfg.wait_c = (op->dummy.nbytes * (BITS_PER_BYTE / op->dummy.buswidth)); + + dw_spi_enable_chip(dws, 0); + + dw_spi_update_config(dws, mem->spi, &cfg); + + dw_spi_enable_chip(dws, 1); + return 0; } diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h index 327d037bdb10e..494b830ad1026 100644 --- a/drivers/spi/spi-dw.h +++ b/drivers/spi/spi-dw.h @@ -101,6 +101,9 @@ #define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22) #define DW_PSSI_CTRLR0_SPI_FRF_MASK GENMASK(22, 21) #define DW_SPI_CTRLR0_SPI_FRF_STD_SPI 0x0 +#define DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI 0x1 +#define DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI 0x2 +#define DW_SPI_CTRLR0_SPI_FRF_OCT_SPI 0x3 /* Bit fields in CTRLR1 */ #define DW_SPI_NDF_MASK GENMASK(15, 0) @@ -132,7 +135,13 @@ #define DW_SPI_SPI_CTRLR0_CLK_STRETCH_EN BIT(30) #define DW_SPI_SPI_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11) #define DW_SPI_SPI_CTRLR0_INST_L_MASK GENMASK(9, 8) +#define DW_SPI_SPI_CTRLR0_INST_L_INST_L0 0x0 +#define DW_SPI_SPI_CTRLR0_INST_L_INST_L8 0x2 +#define DW_SPI_SPI_CTRLR0_INST_L_INST_L16 0x3 #define DW_SPI_SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2) +#define DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT0 0x0 +#define DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT1 0x1 +#define DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT2 0x2 /* Mem/DMA operations helpers */ #define DW_SPI_WAIT_RETRIES 5