From patchwork Fri Feb 18 14:59:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 544032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F17B1C433F5 for ; Fri, 18 Feb 2022 15:00:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236665AbiBRPAo (ORCPT ); Fri, 18 Feb 2022 10:00:44 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:50484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236757AbiBRPA0 (ORCPT ); Fri, 18 Feb 2022 10:00:26 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CAE0ECC59; Fri, 18 Feb 2022 06:59:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1645196360; x=1676732360; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MMBmBCezp7nm9x2XqJiN9Nfc5zCWTIcgFPMneJ/ixI0=; b=B89VH70NYOsqOO6aXTkiV57SZYEZx9GRZa8uxbV/iFU+AGVQ5XdRxpGe vW1x3SF+tzRg535BJXBHlpsoaobo+XzHvc1ZAIc6XKnwlhF07gf0ch3Tq DxDcy7Qo5CYzv9npn1yZT+jOtAWjlLpPXpFPx+lzNRJ+uWcUolG0VKBCw j4dzaP2iOn/ZeMwqa9NTxhwobmFmwZdG5RVoueju7ghcvo/83+G2etQU3 Nyin13X7a+f9WcUIeqaHF0PVwHtvhKIR/2V1Z3gVBS2v1n+n7BRgM/glK TdalgeUK1HvTu2VdMYnmErTjVWwhKLIKwtOQ+4sJ8A+1tQXB0lDLTHFXb w==; X-IronPort-AV: E=Sophos;i="5.88,379,1635231600"; d="scan'208";a="162789015" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 18 Feb 2022 07:59:19 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Fri, 18 Feb 2022 07:59:19 -0700 Received: from ROB-ULT-M18064N.mchp-main.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Fri, 18 Feb 2022 07:59:16 -0700 From: Tudor Ambarus To: , , CC: , , , , , , , , , Tudor Ambarus Subject: [PATCH 4/4] mtd: spi-nor: core: Introduce SPI_NOR_DTR_BSWAP16 no_sfdp_flag Date: Fri, 18 Feb 2022 16:59:00 +0200 Message-ID: <20220218145900.1440045-5-tudor.ambarus@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220218145900.1440045-1-tudor.ambarus@microchip.com> References: <20220218145900.1440045-1-tudor.ambarus@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Introduce SPI_NOR_DTR_BSWAP16 flag for flashes that don't define the mandatory BFPT table. When set it indicates that the byte order of 16-bit words is swapped when read in 8D-8D-8D mode compared to 1-1-1 mode. Signed-off-by: Tudor Ambarus Reviewed-by: Michael Walle --- drivers/mtd/spi-nor/core.c | 5 ++++- drivers/mtd/spi-nor/core.h | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 453d8c54d062..c3128a8e1544 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -2572,7 +2572,7 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) { struct spi_nor_flash_parameter *params = nor->params; struct spi_nor_erase_map *map = ¶ms->erase_map; - const u8 no_sfdp_flags = nor->info->no_sfdp_flags; + const u16 no_sfdp_flags = nor->info->no_sfdp_flags; u8 i, erase_mask; if (no_sfdp_flags & SPI_NOR_DUAL_READ) { @@ -2613,6 +2613,9 @@ static void spi_nor_no_sfdp_init_params(struct spi_nor *nor) SPINOR_OP_PP, SNOR_PROTO_8_8_8_DTR); } + if (no_sfdp_flags & SPI_NOR_DTR_BSWAP16) + nor->flags |= SNOR_F_DTR_BSWAP16; + /* * Sector Erase settings. Sort Erase Types in ascending order, with the * smallest erase size starting at BIT(0). diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h index 7c077d41c335..1cb887437193 100644 --- a/drivers/mtd/spi-nor/core.h +++ b/drivers/mtd/spi-nor/core.h @@ -362,6 +362,8 @@ struct spi_nor_fixups { * SPI_NOR_OCTAL_READ: flash supports Octal Read. * SPI_NOR_OCTAL_DTR_READ: flash supports octal DTR Read. * SPI_NOR_OCTAL_DTR_PP: flash supports Octal DTR Page Program. + * SPI_NOR_DTR_BSWAP16: the byte order of 16-bit words is swapped when + * read or written in DTR mode compared to STR mode. * * @fixup_flags: flags that indicate support that can be discovered via SFDP * ideally, but can not be discovered for this particular flash @@ -404,7 +406,7 @@ struct flash_info { #define USE_FSR BIT(10) #define SPI_NOR_XSR_RDY BIT(11) - u8 no_sfdp_flags; + u16 no_sfdp_flags; #define SPI_NOR_SKIP_SFDP BIT(0) #define SECT_4K BIT(1) #define SECT_4K_PMC BIT(2) @@ -413,6 +415,7 @@ struct flash_info { #define SPI_NOR_OCTAL_READ BIT(5) #define SPI_NOR_OCTAL_DTR_READ BIT(6) #define SPI_NOR_OCTAL_DTR_PP BIT(7) +#define SPI_NOR_DTR_BSWAP16 BIT(8) u8 fixup_flags; #define SPI_NOR_4B_OPCODES BIT(0)