From patchwork Tue Jan 4 08:36:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Miquel Raynal X-Patchwork-Id: 529993 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CBC15C433F5 for ; Tue, 4 Jan 2022 08:36:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232743AbiADIgl (ORCPT ); Tue, 4 Jan 2022 03:36:41 -0500 Received: from relay5-d.mail.gandi.net ([217.70.183.197]:37763 "EHLO relay5-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229677AbiADIgl (ORCPT ); Tue, 4 Jan 2022 03:36:41 -0500 Received: (Authenticated sender: miquel.raynal@bootlin.com) by relay5-d.mail.gandi.net (Postfix) with ESMTPSA id C5F091C000C; Tue, 4 Jan 2022 08:36:38 +0000 (UTC) From: Miquel Raynal To: Richard Weinberger , Vignesh Raghavendra , Tudor Ambarus , Pratyush Yadav , Michael Walle , , Mark Brown , Cc: Julien Su , Jaime Liao , Thomas Petazzoni , Boris Brezillon , Xiangsheng Hou , Miquel Raynal Subject: [PATCH v9 03/13] spi: cadence-quadspi: Provide a capability structure Date: Tue, 4 Jan 2022 09:36:21 +0100 Message-Id: <20220104083631.40776-4-miquel.raynal@bootlin.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220104083631.40776-1-miquel.raynal@bootlin.com> References: <20220104083631.40776-1-miquel.raynal@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This controller has DTR support, so advertize it with a capability now that the spi-controller structure contains this new field. This will later be used by the core to discriminate whether an operation is supported or not, in a more generic way than having different helpers. Signed-off-by: Miquel Raynal Reviewed-by: Pratyush Yadav --- drivers/spi/spi-cadence-quadspi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 101cc71bffa7..6705bbca12a6 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -1394,6 +1394,10 @@ static const struct spi_controller_mem_ops cqspi_mem_ops = { .supports_op = cqspi_supports_mem_op, }; +static const struct spi_controller_mem_caps cqspi_mem_caps = { + .dtr = true, +}; + static int cqspi_setup_flash(struct cqspi_st *cqspi) { struct platform_device *pdev = cqspi->pdev; @@ -1451,6 +1455,7 @@ static int cqspi_probe(struct platform_device *pdev) } master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; master->mem_ops = &cqspi_mem_ops; + master->mem_caps = &cqspi_mem_caps; master->dev.of_node = pdev->dev.of_node; cqspi = spi_master_get_devdata(master);