From patchwork Sat Jan 1 07:42:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Apurva Nandan X-Patchwork-Id: 529539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D800C433F5 for ; Sat, 1 Jan 2022 07:43:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231192AbiAAHnk (ORCPT ); Sat, 1 Jan 2022 02:43:40 -0500 Received: from lelv0142.ext.ti.com ([198.47.23.249]:57956 "EHLO lelv0142.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231136AbiAAHnk (ORCPT ); Sat, 1 Jan 2022 02:43:40 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2017h3DX034524; Sat, 1 Jan 2022 01:43:03 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1641022983; bh=sxImKlYR9bxi/r/0O9cHejg8wu1LEinRPbVkHanMnrk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=OS12gKsGcZA4+GtYSGTk6lZX3VIT4G5t0CJoj84jDPzOXAjsXqKIhL/xnCVwZeZyK V7rl+52Vp2+RQJI/wCSfqR6ZfDwh6bPVQ+7n22DnubW7mc5ChDghxb/6n/0kjZUBQC 6qlT+CDNH+EOKsf7jPCk1BczmlhJZKgWeC3VxZtY= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2017h2JR038760 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 1 Jan 2022 01:43:03 -0600 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Sat, 1 Jan 2022 01:43:02 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Sat, 1 Jan 2022 01:43:02 -0600 Received: from LT5CD112GSQZ.ent.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2017gpwW033162; Sat, 1 Jan 2022 01:42:57 -0600 From: Apurva Nandan To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Mark Brown , Apurva Nandan , Patrice Chotard , Christophe Kerello , Boris Brezillon , Daniel Palmer , Alexander Lobakin , , , CC: Subject: [PATCH v3 01/17] spi: spi-mem: Add DTR templates for cmd, address, dummy and data phase Date: Sat, 1 Jan 2022 13:12:34 +0530 Message-ID: <20220101074250.14443-2-a-nandan@ti.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220101074250.14443-1-a-nandan@ti.com> References: <20220101074250.14443-1-a-nandan@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Setting dtr field of spi_mem_op is useful when creating templates for DTR ops in spinand.h. Also, 2 bytes cmd phases are required when operating in Octal DTR SPI mode. Create new templates for dtr mode cmd, address, dummy and data phase in spi_mem_op, which set the dtr field to 1 and also allow passing the nbytes for the cmd phase. Signed-off-by: Apurva Nandan --- include/linux/spi/spi-mem.h | 41 +++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h index 85e2ff7b840d..682378a9c600 100644 --- a/include/linux/spi/spi-mem.h +++ b/include/linux/spi/spi-mem.h @@ -20,6 +20,14 @@ .nbytes = 1, \ } +#define SPI_MEM_OP_CMD_DTR(__nbytes, __opcode, __buswidth) \ + { \ + .nbytes = __nbytes, \ + .opcode = __opcode, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_ADDR(__nbytes, __val, __buswidth) \ { \ .nbytes = __nbytes, \ @@ -27,6 +35,14 @@ .buswidth = __buswidth, \ } +#define SPI_MEM_OP_ADDR_DTR(__nbytes, __val, __buswidth) \ + { \ + .nbytes = __nbytes, \ + .val = __val, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_NO_ADDR { } #define SPI_MEM_OP_DUMMY(__nbytes, __buswidth) \ @@ -35,6 +51,13 @@ .buswidth = __buswidth, \ } +#define SPI_MEM_OP_DUMMY_DTR(__nbytes, __buswidth) \ + { \ + .nbytes = __nbytes, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_NO_DUMMY { } #define SPI_MEM_OP_DATA_IN(__nbytes, __buf, __buswidth) \ @@ -45,6 +68,15 @@ .buswidth = __buswidth, \ } +#define SPI_MEM_OP_DATA_IN_DTR(__nbytes, __buf, __buswidth) \ + { \ + .dir = SPI_MEM_DATA_IN, \ + .nbytes = __nbytes, \ + .buf.in = __buf, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_DATA_OUT(__nbytes, __buf, __buswidth) \ { \ .dir = SPI_MEM_DATA_OUT, \ @@ -53,6 +85,15 @@ .buswidth = __buswidth, \ } +#define SPI_MEM_OP_DATA_OUT_DTR(__nbytes, __buf, __buswidth) \ + { \ + .dir = SPI_MEM_DATA_OUT, \ + .nbytes = __nbytes, \ + .buf.out = __buf, \ + .buswidth = __buswidth, \ + .dtr = 1, \ + } + #define SPI_MEM_OP_NO_DATA { } /**