diff mbox series

[v3,7/7] spi: dw: Define the capabilities in a continuous bit-flags set

Message ID 20211115181917.7521-8-Sergey.Semin@baikalelectronics.ru
State Accepted
Commit 44ebcb44584f81d1d38fafb45cf57d651f44616e
Headers show
Series spi: dw: Cleanup macros/funcs naming and add IP-core version support | expand

Commit Message

Serge Semin Nov. 15, 2021, 6:19 p.m. UTC
Since the DW_SPI_CAP_DWC_HSSI capability has just been replaced with using
the DW SSI IP-core versions interface, the DW SPI capability flags are now
represented with a gap. Let's fix it by redefining the DW_SPI_CAP_DFS32
macro to setting BIT(2) of the capabilities field.

Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>

---

Changelog v3:
- This is a new patch unpinned from the previous one as of Andy
  suggested.
---
 drivers/spi/spi-dw.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 8334e6b35f89..d5ee5130601e 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -32,7 +32,7 @@ 
 /* DW SPI controller capabilities */
 #define DW_SPI_CAP_CS_OVERRIDE		BIT(0)
 #define DW_SPI_CAP_KEEMBAY_MST		BIT(1)
-#define DW_SPI_CAP_DFS32		BIT(3)
+#define DW_SPI_CAP_DFS32		BIT(2)
 
 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
 #define DW_SPI_CTRLR0			0x00