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[76.183.134.35]) by smtp.gmail.com with ESMTPSA id k16sm523440otp.19.2021.06.04.08.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Jun 2021 08:11:15 -0700 (PDT) From: Chris Morgan To: linux-spi@vger.kernel.org Cc: jon.lin@rock-chips.com, broonie@kernel.org, robh+dt@kernel.org, heiko@sntech.de, jbx6244@gmail.com, hjc@rock-chips.com, yifeng.zhao@rock-chips.com, sugar.zhang@rock-chips.com, linux-rockchip@lists.infradead.org, linux-mtd@lists.infradead.org, p.yadav@ti.com, Chris Morgan Subject: [RFC v4 6/8] arm: dts: rockchip: Add SFC to RV1108 Date: Fri, 4 Jun 2021 10:10:53 -0500 Message-Id: <20210604151055.28636-7-macroalpha82@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210604151055.28636-1-macroalpha82@gmail.com> References: <20210604151055.28636-1-macroalpha82@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Chris Morgan Add a devicetree entry for the Rockchip SFC for the RV1108 SOC. Signed-off-by: Chris Morgan --- arch/arm/boot/dts/rv1108.dtsi | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi index 884872ca5207..c0d95e13add4 100644 --- a/arch/arm/boot/dts/rv1108.dtsi +++ b/arch/arm/boot/dts/rv1108.dtsi @@ -536,6 +536,17 @@ usb_otg: usb@30180000 { status = "disabled"; }; + sfc: spi@301c0000 { + compatible = "rockchip,rv1108-sfc", "rockchip,rk3036-sfc"; + reg = <0x301c0000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SFC>, <&cru SCLK_SFC>; + clock-names = "ahb", "sfc"; + pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>; + pinctrl-names = "default"; + status = "disabled"; + }; + gmac: eth@30200000 { compatible = "rockchip,rv1108-gmac"; reg = <0x30200000 0x10000>; @@ -704,6 +715,32 @@ emmc_cmd: emmc-cmd { }; }; + serial_flash { + sfc_bus4: sfc-bus4 { + rockchip,pins = + <2 RK_PA0 3 &pcfg_pull_none>, + <2 RK_PA1 3 &pcfg_pull_none>, + <2 RK_PA2 3 &pcfg_pull_none>, + <2 RK_PA3 3 &pcfg_pull_none>; + }; + + sfc_bus2: sfc-bus2 { + rockchip,pins = + <2 RK_PA0 3 &pcfg_pull_none>, + <2 RK_PA1 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = + <2 RK_PB4 3 &pcfg_pull_none>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = + <2 RK_PB7 2 &pcfg_pull_none>; + }; + }; + gmac { rmii_pins: rmii-pins { rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,