@@ -39,6 +39,22 @@ &sdhci0 {
microchip,clock-delay = <10>;
};
+&spi0 {
+ status = "okay";
+ spi@0 {
+ compatible = "spi-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>; /* CS0 */
+ spi-flash@9 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0x9>; /* SPI */
+ };
+ };
+};
+
&i2c1 {
status = "okay";
};
@@ -38,6 +38,22 @@ gpio-restart {
};
};
+&spi0 {
+ status = "okay";
+ spi@0 {
+ compatible = "spi-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>; /* CS0 */
+ spi-flash@9 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0x9>; /* SPI */
+ };
+ };
+};
+
&gpio {
i2cmux_pins_i: i2cmux-pins-i {
pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
@@ -51,6 +51,22 @@ i2cmux_s32: i2cmux-3 {
};
};
+&spi0 {
+ status = "okay";
+ spi@0 {
+ compatible = "spi-mux";
+ mux-controls = <&mux>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>; /* CS0 */
+ spi-flash@9 {
+ compatible = "jedec,spi-nor";
+ spi-max-frequency = <8000000>;
+ reg = <0x9>; /* SPI */
+ };
+ };
+};
+
&axi {
i2c0_imux: i2c0-imux@0 {
compatible = "i2c-mux-pinctrl";
This add spi-nor device nodes to the Sparx5 reference boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> --- arch/arm64/boot/dts/microchip/sparx5_pcb125.dts | 16 ++++++++++++++++ .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 16 ++++++++++++++++ .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 16 ++++++++++++++++ 3 files changed, 48 insertions(+)