diff mbox series

[v3,1/9] dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM

Message ID 1607721363-8879-2-git-send-email-skomatineni@nvidia.com
State Superseded
Headers show
Series [v3,1/9] dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM | expand

Commit Message

Sowjanya Komatineni Dec. 11, 2020, 9:15 p.m. UTC
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled
when using DDR interface mode.

This patch adds clock ID for this to dt-binding.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 include/dt-bindings/clock/tegra210-car.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Rob Herring (Arm) Dec. 15, 2020, 4:03 p.m. UTC | #1
On Fri, 11 Dec 2020 13:15:55 -0800, Sowjanya Komatineni wrote:
> Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled

> when using DDR interface mode.

> 

> This patch adds clock ID for this to dt-binding.

> 

> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>

> ---

>  include/dt-bindings/clock/tegra210-car.h | 2 +-

>  1 file changed, 1 insertion(+), 1 deletion(-)

> 


Acked-by: Rob Herring <robh@kernel.org>
diff mbox series

Patch

diff --git a/include/dt-bindings/clock/tegra210-car.h b/include/dt-bindings/clock/tegra210-car.h
index ab8b8a7..9cfcc3b 100644
--- a/include/dt-bindings/clock/tegra210-car.h
+++ b/include/dt-bindings/clock/tegra210-car.h
@@ -307,7 +307,7 @@ 
 #define TEGRA210_CLK_AUDIO4 275
 #define TEGRA210_CLK_SPDIF 276
 /* 277 */
-/* 278 */
+#define TEGRA210_CLK_QSPI_PM 278
 /* 279 */
 /* 280 */
 #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */