| Message ID | 1606857168-5839-3-git-send-email-skomatineni@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add Tegra QSPI driver | expand |
On 12/9/20 9:26 AM, Rob Herring wrote: > On Tue, Dec 01, 2020 at 01:12:43PM -0800, Sowjanya Komatineni wrote: >> This patch adds YAML based device tree binding document for Tegra >> QSPI driver. >> >> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> >> --- >> .../devicetree/bindings/spi/nvidia,tegra-qspi.yaml | 77 ++++++++++++++++++++++ >> 1 file changed, 77 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra-qspi.yaml >> >> diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra-qspi.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra-qspi.yaml >> new file mode 100644 >> index 0000000..038a085 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra-qspi.yaml >> @@ -0,0 +1,77 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/spi/nvidia,tegra-qspi.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Tegra Quad SPI Controller >> + >> +maintainers: >> + - Thierry Reding <thierry.reding@gmail.com> >> + - Jonathan Hunter <jonathanh@nvidia.com> >> + >> +properties: >> + compatible: >> + enum: >> + - nvidia,tegra210-qspi >> + - nvidia,tegra186-qspi >> + - nvidia,tegra194-qspi >> + >> + reg: >> + items: >> + - description: QSPI registers > Just 'maxItems: 1' > >> + >> + interrupts: >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: qspi > Kind of a pointless name. Thanks Rob for feedback. Do you mean to change name something like qspi-clk instead of qspi? > >> + >> + clocks: >> + maxItems: 1 >> + >> + reset-names: >> + minItems: 1 >> + items: >> + - const: qspi > Same here. > >> + >> + resets: >> + maxItems: 1 >> + >> + dmas: >> + maxItems: 2 >> + >> + dma-names: >> + items: >> + - const: rx >> + - const: tx >> + >> +required: >> + - compatible >> + - reg >> + - interrupts >> + - clock-names >> + - clocks >> + - reset-names >> + - resets >> + >> +additionalProperties: true >> + >> +examples: >> + - | >> + #include <dt-bindings/clock/tegra210-car.h> >> + #include <dt-bindings/reset/tegra210-car.h> >> + #include <dt-bindings/interrupt-controller/arm-gic.h> >> + >> + spi@70410000 { >> + compatible = "nvidia,tegra210-qspi"; >> + reg = <0x70410000 0x1000>; >> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&tegra_car TEGRA210_CLK_QSPI>; >> + clock-names = "qspi"; >> + resets = <&tegra_car 211>; >> + reset-names = "qspi"; >> + dmas = <&apbdma 5>, <&apbdma 5>; >> + dma-names = "rx", "tx"; >> + }; >> -- >> 2.7.4 >>
diff --git a/Documentation/devicetree/bindings/spi/nvidia,tegra-qspi.yaml b/Documentation/devicetree/bindings/spi/nvidia,tegra-qspi.yaml new file mode 100644 index 0000000..038a085 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nvidia,tegra-qspi.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nvidia,tegra-qspi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra Quad SPI Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jonathan Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra210-qspi + - nvidia,tegra186-qspi + - nvidia,tegra194-qspi + + reg: + items: + - description: QSPI registers + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: qspi + + clocks: + maxItems: 1 + + reset-names: + minItems: 1 + items: + - const: qspi + + resets: + maxItems: 1 + + dmas: + maxItems: 2 + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - reset-names + - resets + +additionalProperties: true + +examples: + - | + #include <dt-bindings/clock/tegra210-car.h> + #include <dt-bindings/reset/tegra210-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + spi@70410000 { + compatible = "nvidia,tegra210-qspi"; + reg = <0x70410000 0x1000>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA210_CLK_QSPI>; + clock-names = "qspi"; + resets = <&tegra_car 211>; + reset-names = "qspi"; + dmas = <&apbdma 5>, <&apbdma 5>; + dma-names = "rx", "tx"; + };
This patch adds YAML based device tree binding document for Tegra QSPI driver. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- .../devicetree/bindings/spi/nvidia,tegra-qspi.yaml | 77 ++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/nvidia,tegra-qspi.yaml