From patchwork Wed Nov 9 10:39:22 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 4971 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 3679F23E0E for ; Wed, 9 Nov 2011 10:39:51 +0000 (UTC) Received: from mail-fx0-f52.google.com (mail-fx0-f52.google.com [209.85.161.52]) by fiordland.canonical.com (Postfix) with ESMTP id 251A6A180CE for ; Wed, 9 Nov 2011 10:39:51 +0000 (UTC) Received: by mail-fx0-f52.google.com with SMTP id n26so2131830faa.11 for ; Wed, 09 Nov 2011 02:39:51 -0800 (PST) Received: by 10.152.106.130 with SMTP id gu2mr1109386lab.37.1320835190912; Wed, 09 Nov 2011 02:39:50 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.152.10.72 with SMTP id g8cs163020lab; Wed, 9 Nov 2011 02:39:50 -0800 (PST) Received: by 10.213.28.68 with SMTP id l4mr162967ebc.58.1320835189404; Wed, 09 Nov 2011 02:39:49 -0800 (PST) Received: from eu1sys200aog102.obsmtp.com (eu1sys200aog102.obsmtp.com. [207.126.144.113]) by mx.google.com with SMTP id p2si1079888eef.132.2011.11.09.02.39.27 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 09 Nov 2011 02:39:49 -0800 (PST) Received-SPF: neutral (google.com: 207.126.144.113 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.113; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.113 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-us.st.com ([167.4.1.35]) (using TLSv1) by eu1sys200aob102.postini.com ([207.126.147.11]) with SMTP ID DSNKTrpYXzoumWKKtHluqK4qaAWL8PYm0FV0@postini.com; Wed, 09 Nov 2011 10:39:36 UTC Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 7ED0F79; Wed, 9 Nov 2011 10:39:25 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 90E703F; Wed, 9 Nov 2011 10:38:39 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 5C5ED24C075; Wed, 9 Nov 2011 11:39:19 +0100 (CET) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Wed, 9 Nov 2011 11:39:24 +0100 From: Linus Walleij To: Grant Likely , Cc: , Viresh Kumar , Chris Blair , Linus Walleij Subject: [PATCH 5/6] spi/pl022: move device disable to workqueue thread Date: Wed, 9 Nov 2011 11:39:22 +0100 Message-ID: <1320835162-31337-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Chris Blair Moves the disabling of the device and clocks to the same thread in which the device and clocks are enabled. This avoids SMP issues where the device can be enabled for a transfer by one thread and then disabled by the completion of the previous transfer in another thread. Signed-off-by: Chris Blair Signed-off-by: Linus Walleij --- drivers/spi/spi-pl022.c | 33 +++++++++++++++++++-------------- 1 files changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index bffad2a..2e3522d 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -512,13 +512,6 @@ static void giveback(struct pl022 *pl022) msg->state = NULL; if (msg->complete) msg->complete(msg->context); - - /* disable the SPI/SSP operation */ - writew((readw(SSP_CR1(pl022->virtbase)) & - (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); - - /* This message is completed, so let's turn off the clocks & power */ - pm_runtime_put(&pl022->adev->dev); } /** @@ -1513,10 +1506,17 @@ static void pump_messages(struct work_struct *work) struct pl022 *pl022 = container_of(work, struct pl022, pump_messages); unsigned long flags; + bool was_busy = false; /* Lock queue and check for queue work */ spin_lock_irqsave(&pl022->queue_lock, flags); if (list_empty(&pl022->queue) || !pl022->running) { + if (pl022->busy) { + /* nothing more to do - disable spi/ssp and power off */ + writew((readw(SSP_CR1(pl022->virtbase)) & + (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase)); + pm_runtime_put(&pl022->adev->dev); + } pl022->busy = false; spin_unlock_irqrestore(&pl022->queue_lock, flags); return; @@ -1531,7 +1531,10 @@ static void pump_messages(struct work_struct *work) list_entry(pl022->queue.next, struct spi_message, queue); list_del_init(&pl022->cur_msg->queue); - pl022->busy = true; + if (pl022->busy) + was_busy = true; + else + pl022->busy = true; spin_unlock_irqrestore(&pl022->queue_lock, flags); /* Initial message state */ @@ -1541,12 +1544,14 @@ static void pump_messages(struct work_struct *work) /* Setup the SPI using the per chip configuration */ pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi); - /* - * We enable the core voltage and clocks here, then the clocks - * and core will be disabled when giveback() is called in each method - * (poll/interrupt/DMA) - */ - pm_runtime_get_sync(&pl022->adev->dev); + if (!was_busy) + /* + * We enable the core voltage and clocks here, then the clocks + * and core will be disabled when this workqueue is run again + * and there is no more work to be done. + */ + pm_runtime_get_sync(&pl022->adev->dev); + restore_state(pl022); flush(pl022);