From patchwork Thu Jun 16 08:14:28 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 1964 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 7CD4024B1B for ; Thu, 16 Jun 2011 08:14:54 +0000 (UTC) Received: from mail-vx0-f180.google.com (mail-vx0-f180.google.com [209.85.220.180]) by fiordland.canonical.com (Postfix) with ESMTP id 2D281A18081 for ; Thu, 16 Jun 2011 08:14:54 +0000 (UTC) Received: by vxk12 with SMTP id 12so1375241vxk.11 for ; Thu, 16 Jun 2011 01:14:53 -0700 (PDT) Received: by 10.52.98.97 with SMTP id eh1mr882782vdb.7.1308212093622; Thu, 16 Jun 2011 01:14:53 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.52.183.130 with SMTP id em2cs172139vdc; Thu, 16 Jun 2011 01:14:53 -0700 (PDT) Received: by 10.213.26.217 with SMTP id f25mr286696ebc.104.1308212092317; Thu, 16 Jun 2011 01:14:52 -0700 (PDT) Received: from eu1sys200aog101.obsmtp.com (eu1sys200aog101.obsmtp.com [207.126.144.111]) by mx.google.com with SMTP id p8si852288eep.82.2011.06.16.01.14.41 (version=TLSv1/SSLv3 cipher=OTHER); Thu, 16 Jun 2011 01:14:52 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.111 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.111; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.111 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob101.postini.com ([207.126.147.11]) with SMTP ID DSNKTfm7cKD7P0MlQlT/eKoLfyGn+VRbMoqB@postini.com; Thu, 16 Jun 2011 08:14:51 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 268B7160; Thu, 16 Jun 2011 08:14:36 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 98913A9A; Thu, 16 Jun 2011 08:14:35 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 0E14D24C07C; Thu, 16 Jun 2011 10:14:30 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Thu, 16 Jun 2011 10:14:34 +0200 From: Linus Walleij To: Grant Likely , Cc: Lee Jones , Linus Walleij Subject: [PATCH 1/4] spi/pl022: initialize burstsize from FIFO trigger level Date: Thu, 16 Jun 2011 10:14:28 +0200 Message-ID: <1308212068-22472-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Linus Walleij Configure the DMA burstsize from the FIFO trigger level supplied with the controller configuration data. This is based on a patch from Virupax, but I rewrote it differently. Reported-by: Virupax Sadashivpetimath Signed-off-by: Linus Walleij --- drivers/spi/spi-pl022.c | 55 +++++++++++++++++++++++++++++++++++++++++++++- 1 files changed, 53 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c index b3bd8d8..ac7c727 100644 --- a/drivers/spi/spi-pl022.c +++ b/drivers/spi/spi-pl022.c @@ -381,6 +381,8 @@ struct pl022 { enum ssp_reading read; enum ssp_writing write; u32 exp_fifo_level; + enum ssp_rx_level_trig rx_lev_trig; + enum ssp_tx_level_trig tx_lev_trig; /* DMA settings */ #ifdef CONFIG_DMA_ENGINE struct dma_chan *dma_rx_channel; @@ -907,12 +909,10 @@ static int configure_dma(struct pl022 *pl022) struct dma_slave_config rx_conf = { .src_addr = SSP_DR(pl022->phybase), .direction = DMA_FROM_DEVICE, - .src_maxburst = pl022->vendor->fifodepth >> 1, }; struct dma_slave_config tx_conf = { .dst_addr = SSP_DR(pl022->phybase), .direction = DMA_TO_DEVICE, - .dst_maxburst = pl022->vendor->fifodepth >> 1, }; unsigned int pages; int ret; @@ -926,6 +926,54 @@ static int configure_dma(struct pl022 *pl022) if (!rxchan || !txchan) return -ENODEV; + /* + * If supplied, the DMA burstsize should equal the FIFO trigger level. + * Notice that the DMA engine uses one-to-one mapping. Since we can + * not trigger on 2 elements this needs explicit mapping rather than + * calculation. + */ + switch (pl022->rx_lev_trig) { + case SSP_RX_1_OR_MORE_ELEM: + rx_conf.src_maxburst = 1; + break; + case SSP_RX_4_OR_MORE_ELEM: + rx_conf.src_maxburst = 4; + break; + case SSP_RX_8_OR_MORE_ELEM: + rx_conf.src_maxburst = 8; + break; + case SSP_RX_16_OR_MORE_ELEM: + rx_conf.src_maxburst = 16; + break; + case SSP_RX_32_OR_MORE_ELEM: + rx_conf.src_maxburst = 32; + break; + default: + rx_conf.src_maxburst = pl022->vendor->fifodepth >> 1; + break; + } + + switch (pl022->tx_lev_trig) { + case SSP_TX_1_OR_MORE_EMPTY_LOC: + tx_conf.dst_maxburst = 1; + break; + case SSP_TX_4_OR_MORE_EMPTY_LOC: + tx_conf.dst_maxburst = 4; + break; + case SSP_TX_8_OR_MORE_EMPTY_LOC: + tx_conf.dst_maxburst = 8; + break; + case SSP_TX_16_OR_MORE_EMPTY_LOC: + tx_conf.dst_maxburst = 16; + break; + case SSP_TX_32_OR_MORE_EMPTY_LOC: + tx_conf.dst_maxburst = 32; + break; + default: + tx_conf.dst_maxburst = pl022->vendor->fifodepth >> 1; + break; + } + switch (pl022->read) { case READING_NULL: /* Use the same as for writing */ @@ -1872,6 +1920,9 @@ static int pl022_setup(struct spi_device *spi) goto err_config_params; } + pl022->rx_lev_trig = chip_info->rx_lev_trig; + pl022->tx_lev_trig = chip_info->tx_lev_trig; + /* Now set controller state based on controller data */ chip->xfer_type = chip_info->com_mode; if (!chip_info->cs_control) {