From patchwork Tue Jul 18 06:57:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Durai Manickam KR X-Patchwork-Id: 704297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A2ED1C001DC for ; Tue, 18 Jul 2023 06:57:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231491AbjGRG56 (ORCPT ); Tue, 18 Jul 2023 02:57:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229705AbjGRG5y (ORCPT ); Tue, 18 Jul 2023 02:57:54 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A54B21A2; Mon, 17 Jul 2023 23:57:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1689663473; x=1721199473; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=KB6wQi2fSkHzaNEB8uUFd6EhlNuh6Xp2A6Y58nxMss0=; b=D80q7/QZ3vJvftcynOekJbUHbFnM4XFUETdqyjpD17eusU/ZJA2v3RBj MlB2pBWGIQjEbsiANHjJ1F1l8AQNk6R1axDHOTr/zFOMigebJmcyjCCOR pBJnhI3OniJhQM6ooti4CCehcthToPKfcNYP/D52sfU9vfAoStDOw7GxK BMvBYTWSTJJ+ADyeBU8BVpW/j4AUdmPDWovEbKh6Xt3M/OQFIpCV7agf1 cXAREcYSPXTn2DU75v844koz3Wmd19noZrpQj3SBt9K6gnhDKOpddypqr pD/iwx/NuQ7lX12eHz9sBeaNyOaGYnKZGueL9I21Aw2bQ3GBRCGmnFeov g==; X-IronPort-AV: E=Sophos;i="6.01,213,1684825200"; d="scan'208";a="224388338" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Jul 2023 23:57:52 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 17 Jul 2023 23:57:50 -0700 Received: from che-lt-i66125lx.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 17 Jul 2023 23:57:39 -0700 From: Durai Manickam KR To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Durai Manickam KR Subject: [PATCHv3 0/2] update at91 usart compatible for sam9x60 Date: Tue, 18 Jul 2023 12:27:33 +0530 Message-ID: <20230718065735.10187-1-durai.manickamkr@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org There is only one debug unit in the sam9x60 SOC and it has the chipid register. So defining these dbgu compatible strings to the flexcom usart is not correct and causes the SOC detection failure. So removing these dbgu compatible strings defined under the flexcom usart and updating the yaml file accordingly. --- v2 changes: 1. Updating the dt-bindings documentation and send one more patch for the yaml file. --- v3 change: 1. Explained the issue in the commit message rather than in the cover letter. Added the detailed commit message for the changes done. --- Durai Manickam KR (2): dt-bindings: serial: atmel,at91-usart: update compatible for sam9x60 ARM: dts: at91: sam9x60: fix the SOC detection .../bindings/serial/atmel,at91-usart.yaml | 4 ++- arch/arm/boot/dts/microchip/sam9x60.dtsi | 26 +++++++++---------- 2 files changed, 16 insertions(+), 14 deletions(-)