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Mon, 20 Mar 2023 05:03:05 -0500 From: Sai Krishna Potthuri To: Mark Brown CC: , , , , Sai Krishna Potthuri Subject: [PATCH 0/2] spi: cadence-quadspi: Fix random issues with Xilinx Versal DMA read Date: Mon, 20 Mar 2023 15:29:29 +0530 Message-ID: <20230320095931.2651714-1-sai.krishna.potthuri@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT064:EE_|PH8PR12MB7421:EE_ X-MS-Office365-Filtering-Correlation-Id: e4001432-3b3e-4b71-7aa9-08db292a4e0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +8SxvrwT6OaeFoTk4mQ74KkHPyouVRznr0CwNy8R/QahtGyPXRpZ9XHg9EfERU9Ww+TJ3a4qmLJaVF/JnJSMV6i0vYdnwQg+Kx8nfAe0imO1XmNymPX7t39CvEVIWaCFwiUiFzmGoO96SN/WoBizX41i90gWuB28F1SVpjxpyhD+kglVtdWx1NCFlQwLYVDkZY4EZ+QhjiZqKhXodYpBv/+Cc1m9Iex/LFSFoXSMuTS5++OZIOUEODVl99FnALOVJbT1oBCEjuTU9KeqOouVm7dECuQG76hBDkrDIiSErjo3+6G/RUQqOZRwRLv1AIhqEZgix5dpLb2EmvYB+G5UzpN35T8P71JA/rG7MfHiZahf3f/6A3Io4gQ8NXctx/QbEk3M0BRcSpXCtTBy+m6tZpsJsp7tq3aZMRFpTQMF53Ks509qetvO1YEYxdGxTSGeyS68J32s+jw/uy/GWsLxw1fmSIkQBTZcOPJ1TRqbvILtc/kjnTSSfidmJi9VSBoTWJjKPz5GCLOT0vX2LnJiuIsMo4C/Rm6Q5GAa+SbxqCPl1vEzYQtHLfza/a5wEN7k15RssuH/4phTNzYb3lA+aj/x/TRZHhAxaLxV9rliWebRdhkNlaIdwFlnKCFdzL9H7NF8tVYsvGgpnl/OfwuLSVBS1fapFyL6qJQaMQTBD5HCaaR5i+R9TNrdoquraXQuFVCTQcv6zFOQRlVgkd/17tJzoR5kP72wUNG9KEBoI9c= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230025)(4636009)(39860400002)(136003)(376002)(396003)(346002)(451199018)(46966006)(36840700001)(40470700004)(103116003)(86362001)(478600001)(82310400005)(316002)(54906003)(356005)(70206006)(70586007)(4326008)(8676002)(6916009)(6666004)(186003)(1076003)(41300700001)(26005)(81166007)(82740400003)(40480700001)(5660300002)(40460700003)(36756003)(4744005)(8936002)(2616005)(336012)(2906002)(83380400001)(47076005)(426003)(36860700001)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Mar 2023 10:03:07.7081 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4001432-3b3e-4b71-7aa9-08db292a4e0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT064.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7421 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Update Xilinx Versal external DMA read logic to fix random issues - Instead of having the fixed timeout, update the read timeout based on the length of the transfer to avoid timeout for larger data size. - While switching between external DMA read and indirect read, disable the SPI before configuration and enable it after configuration as recommended by Octal-SPI Flash Controller specification. Sai Krishna Potthuri (2): spi: cadence-quadspi: Update the read timeout based on the length spi: cadence-quadspi: Disable the SPI before reconfiguring drivers/spi/spi-cadence-quadspi.c | 40 ++++++++++++++++++------------- 1 file changed, 24 insertions(+), 16 deletions(-)