| Message ID | 20230320095931.2651714-1-sai.krishna.potthuri@amd.com |
|---|---|
| Headers | show |
| Series | spi: cadence-quadspi: Fix random issues with Xilinx Versal DMA read | expand |
> -----Original Message----- > From: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com> > Sent: Monday, March 20, 2023 3:29 PM > To: Mark Brown <broonie@kernel.org> > Cc: linux-spi@vger.kernel.org; linux-kernel@vger.kernel.org; git (AMD-Xilinx) > <git@amd.com>; saikrishna12468@gmail.com; Potthuri, Sai Krishna > <sai.krishna.potthuri@amd.com> > Subject: [PATCH 0/2] spi: cadence-quadspi: Fix random issues with Xilinx Versal > DMA read > > Update Xilinx Versal external DMA read logic to fix random issues > - Instead of having the fixed timeout, update the read timeout based on the > length of the transfer to avoid timeout for larger data size. > - While switching between external DMA read and indirect read, disable the SPI > before configuration and enable it after configuration as recommended by Octal- > SPI Flash Controller specification. > > Sai Krishna Potthuri (2): > spi: cadence-quadspi: Update the read timeout based on the length > spi: cadence-quadspi: Disable the SPI before reconfiguring > > drivers/spi/spi-cadence-quadspi.c | 40 ++++++++++++++++++------------- > 1 file changed, 24 insertions(+), 16 deletions(-) > > -- Mark: Do you have any comments on this series? Regards Sai Krishna
On Fri, Apr 14, 2023 at 06:05:15AM +0000, Potthuri, Sai Krishna wrote:
> Mark: Do you have any comments on this series?
Please don't send content free pings and please allow a reasonable time
for review. People get busy, go on holiday, attend conferences and so
on so unless there is some reason for urgency (like critical bug fixes)
please allow at least a couple of weeks for review. If there have been
review comments then people may be waiting for those to be addressed.
Sending content free pings adds to the mail volume (if they are seen at
all) which is often the problem and since they can't be reviewed
directly if something has gone wrong you'll have to resend the patches
anyway, so sending again is generally a better approach though there are
some other maintainers who like them - if in doubt look at how patches
for the subsystem are normally handled.
On Mon, 20 Mar 2023 15:29:29 +0530, Sai Krishna Potthuri wrote: > Update Xilinx Versal external DMA read logic to fix random issues > - Instead of having the fixed timeout, update the read timeout based on > the length of the transfer to avoid timeout for larger data size. > - While switching between external DMA read and indirect read, disable the > SPI before configuration and enable it after configuration as recommended > by Octal-SPI Flash Controller specification. > > [...] Applied to https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next Thanks! [1/2] spi: cadence-quadspi: Update the read timeout based on the length commit: 22c8ce0aa274cea2ff538ffdf723053ecf77d78b [2/2] spi: cadence-quadspi: Disable the SPI before reconfiguring commit: c0b53f4e545e4c6106aab553eb351138d46211cc All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark