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[v4,0/4] Add support for Microchip QSPI controller

Message ID 20220808064603.1174906-1-nagasuresh.relli@microchip.com
Headers show
Series Add support for Microchip QSPI controller | expand

Message

Naga Sureshkumar Relli Aug. 8, 2022, 6:45 a.m. UTC
This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI
controller support.

Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's
ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI.

changes in v4
-------------
1. Removed microchip,mpfs-qspi compatible from the driver
2. Changed platform_get_irq() return value check from <=0 to <0
3. Fixed dt_binding_check warning by installing latest yamllint

changes in v3
------------
1. Added dev_err_probe() at places like probe failures
2. Split the dt-bindings one for adding coreqspi compatible
   and other one to add coreqspi as fallback to mpfs-qspi.

changes in v2
------------
1. Replaced spi_alloc_master() with devm_spi_alloc_master()
2. Used dev_err_probe() when devm_spi_alloc_master() fails.
3. Added shared IRQ flag in the interrupt registration.
4. Updated the dt_bindings so that there is a differentiation
   between FPGA QSPI IP core and hard QSPI IP core.

Naga Sureshkumar Relli (4):
  spi: dt-binding: document microchip coreQSPI
  spi: dt-binding: add coreqspi as a fallback for mpfs-qspi
  spi: microchip-core-qspi: Add support for microchip fpga qspi
    controllers
  MAINTAINERS: add qspi to Polarfire SoC entry

 .../bindings/spi/microchip,mpfs-spi.yaml      |  15 +-
 MAINTAINERS                                   |   1 +
 drivers/spi/Kconfig                           |   9 +
 drivers/spi/Makefile                          |   1 +
 drivers/spi/spi-microchip-core-qspi.c         | 600 ++++++++++++++++++
 5 files changed, 622 insertions(+), 4 deletions(-)
 create mode 100644 drivers/spi/spi-microchip-core-qspi.c

Comments

Mark Brown Aug. 15, 2022, 3:45 p.m. UTC | #1
On Mon, 8 Aug 2022 12:15:59 +0530, Naga Sureshkumar Relli wrote:
> This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI
> controller support.
> 
> Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's
> ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI.
> 
> changes in v4
> -------------
> 1. Removed microchip,mpfs-qspi compatible from the driver
> 2. Changed platform_get_irq() return value check from <=0 to <0
> 3. Fixed dt_binding_check warning by installing latest yamllint
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/4] spi: dt-binding: document microchip coreQSPI
      commit: a5890c12ecce2696f90ef7d2b8fbb33387f735de
[2/4] spi: dt-binding: add coreqspi as a fallback for mpfs-qspi
      commit: 2ba464e5a3b5743e8f935b5a02b9a7c3d2bd9549
[3/4] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers
      commit: 8596124c4c1bc7561454cee0463c16eca70b5d25
[4/4] MAINTAINERS: add qspi to Polarfire SoC entry
      commit: 1f7d00a7565c8468bbfef87f9fbfebb047003942

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark