From patchwork Tue Aug 2 07:05:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Naga Sureshkumar Relli X-Patchwork-Id: 595297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62FC9C00140 for ; Tue, 2 Aug 2022 07:06:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232871AbiHBHGH (ORCPT ); Tue, 2 Aug 2022 03:06:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232817AbiHBHGE (ORCPT ); Tue, 2 Aug 2022 03:06:04 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 636D9B1E1; Tue, 2 Aug 2022 00:06:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1659423962; x=1690959962; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4uKslXInd/LYsZkf3rMu4R9j6IPobKre4A/4EBr2oP4=; b=WNkiDPnLjTkIyJX5nfX/S7QOHWZYF2bq2NuhVlqBUT1tp/UQG8XU4T8W gDuMmiA9cFJrBO3nImB7M0SmZJ2qNssDhZ7WLkEoEjbnvySBKmTuHzfbL oJkjsTCa9ww0L1tqJuLo7N/fi7sjJjMujPFVyYhNLBFGedXoC3g1scA2U XOetq25LCVYFVAIDgYcdo2HMpygkNscew/RiJLMQJXGCRV5WMlnS0DtmB WEzS5zCXpwHd44LyxYJjGON3hhaAd9TTguxF1nOZ/WVRkvN+s1HrhxEkU VwU+WpakpYDDUDMNJzb2WrzJEPbhrt/cqyeXQgdECFNctqm/BpvNclhsm g==; X-IronPort-AV: E=Sophos;i="5.93,210,1654585200"; d="scan'208";a="174531286" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 02 Aug 2022 00:06:02 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 2 Aug 2022 00:06:00 -0700 Received: from microchip-OptiPlex-5040.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Tue, 2 Aug 2022 00:05:57 -0700 From: Naga Sureshkumar Relli To: , , , CC: , , , Naga Sureshkumar Relli Subject: [PATCH v2 0/3] Add support for Microchip QSPI controller Date: Tue, 2 Aug 2022 12:35:15 +0530 Message-ID: <20220802070518.855951-1-nagasuresh.relli@microchip.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This patch enables the Microchip's FPGA QSPI and Polarfire SoC QSPI controller support. Tested spi-nand (W25N01GV) and spi-nor (MT25QL256A) on Microchip's ICICLE kit. tested using both FPGA QSPI and Polarfie SoC QSPI. changes in v2 ------------ 1. Replaced spi_alloc_master() with devm_spi_alloc_master() 2. Used dev_err_probe() when devm_spi_alloc_master() fails. 3. Added shared IRQ flag in the interrupt registration. 4. Updated the dt_bindings so that there is a differentiation between FPGA QSPI IP core and hard QSPI IP core. 5. Updated the MAINTAINERS file. Naga Sureshkumar Relli (3): spi: dt-binding: add Microchip CoreQSPI compatible spi: microchip-core-qspi: Add support for microchip fpga qspi controllers MAINTAINERS: add qspi to Polarfire SoC entry .../bindings/spi/microchip,mpfs-spi.yaml | 12 +- MAINTAINERS | 1 + drivers/spi/Kconfig | 9 + drivers/spi/Makefile | 1 + drivers/spi/spi-microchip-core-qspi.c | 609 ++++++++++++++++++ 5 files changed, 629 insertions(+), 3 deletions(-) create mode 100644 drivers/spi/spi-microchip-core-qspi.c