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Mon, 6 Jun 2022 04:26:19 -0700 Envelope-to: git@xilinx.com, broonie@kernel.org, p.yadav@ti.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com, linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, michael@walle.cc, linux-mtd@lists.infradead.org Received: from [10.140.6.18] (port=43350 helo=xhdlakshmis40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1nyAsE-0000SR-Qt; Mon, 06 Jun 2022 04:26:19 -0700 From: Amit Kumar Mahapatra To: , , , , CC: , , , , , , , Amit Kumar Mahapatra Subject: [RFC PATCH 0/2] spi: Add support for stacked/parallel memories Date: Mon, 6 Jun 2022 16:56:05 +0530 Message-ID: <20220606112607.20800-1-amit.kumar-mahapatra@xilinx.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 28d63e8f-bab4-46ae-9f9b-08da47af6174 X-MS-TrafficTypeDiagnostic: SN6PR02MB4127:EE_ X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jun 2022 11:26:20.5447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28d63e8f-bab4-46ae-9f9b-08da47af6174 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: SN1NAM02FT0012.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB4127 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org This RFC is the continuation to the discussion which happened on 'commit f89504300e94 ("spi: Stacked/parallel memories bindings")' for adding dtbinding support for stacked/parallel memories. The purpose of this patch series is to demonstrate the changes in spi-nor, spi core and ZynqMP GQSPI driver w.r.t to stacked/parallel memories support.Please go through the series and share you comments. To support stacked/parallel configuration following changes are done to spi core and spi-nor. - The chip select member (chip_select) of the spi_device structure is changed to an array (chip_select[2]). This array is used to store the CS values coming form the "reg" DT property. - Added a new member (cs_index_mask) in the spi_device structure to hold the index information of above chip_select array. SPI-NOR is not aware of the chip_select values, For any incoming request SPI-NOR will decide the flash index with the help of individual flash size and the configuration type (single/stacked/parallel). SPI-NOR will pass on the flash index information to the SPI core by setting the appropriate bit(s) of "cs_index_mask". For example if nth bit of "cs_index_mask" is set then the driver would assert chip_slect[n]. - The flash parameter member(*params) of the spi_nor structure is changed to an array (*params[2]). The array is used to store the parameters of each flash connected in stacked/parallel configuration. This patch series targets flashes of same make connected in stacked configuration and for parallel configuration both the flashes should be identical. --- BRANCH: mtd/next --- Amit Kumar Mahapatra (2): spi: Add multiple CS support for a single SPI device mtd: spi-nor: Add support for stacked/parallel memories drivers/mtd/spi-nor/core.c | 104 +++++++++++++++++++++++++++++---- drivers/mtd/spi-nor/core.h | 5 ++ drivers/spi/spi-zynqmp-gqspi.c | 30 ++++++++-- drivers/spi/spi.c | 10 +++- include/linux/mtd/spi-nor.h | 8 ++- include/linux/spi/spi.h | 10 +++- 6 files changed, 146 insertions(+), 21 deletions(-)