| Message ID | 20220307065230.12655-1-leilk.liu@mediatek.com |
|---|---|
| Headers | show |
| Series | spi: mediatek: add single/quad mode support | expand |
Il 07/03/22 07:52, Leilk Liu ha scritto: > this patch support tick_delay bit[31:30] without enhance_timing feature. > > Fixes: f84d866ab43f("spi: mediatek: add tick_delay support") > Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > drivers/spi/spi-mt65xx.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) > > diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c > index bbfeb8046c17..3fd89548ec3c 100644 > --- a/drivers/spi/spi-mt65xx.c > +++ b/drivers/spi/spi-mt65xx.c > @@ -43,8 +43,11 @@ > #define SPI_CFG1_PACKET_LOOP_OFFSET 8 > #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 > #define SPI_CFG1_GET_TICK_DLY_OFFSET 29 > +#define SPI_CFG1_GET_TICK_DLY_OFFSET_V1 30 > > #define SPI_CFG1_GET_TICK_DLY_MASK 0xe0000000 > +#define SPI_CFG1_GET_TICK_DLY_MASK_V1 0xc0000000 > + > #define SPI_CFG1_CS_IDLE_MASK 0xff > #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 > #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 > @@ -346,9 +349,15 @@ static int mtk_spi_prepare_message(struct spi_master *master, > > /* tick delay */ > reg_val = readl(mdata->base + SPI_CFG1_REG); > - reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; > - reg_val |= ((chip_config->tick_delay & 0x7) > - << SPI_CFG1_GET_TICK_DLY_OFFSET); > + if (mdata->dev_comp->enhance_timing) { > + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK; > + reg_val |= ((chip_config->tick_delay & 0x7) > + << SPI_CFG1_GET_TICK_DLY_OFFSET); > + } else { > + reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1; > + reg_val |= ((chip_config->tick_delay & 0x3) > + << SPI_CFG1_GET_TICK_DLY_OFFSET_V1); > + } > writel(reg_val, mdata->base + SPI_CFG1_REG); > > /* set hw cs timing */
On Mon, 2022-03-07 at 11:32 +0100, AngeloGioacchino Del Regno wrote: > Il 07/03/22 07:52, Leilk Liu ha scritto: > > This patch adds dt-binding documentation for MT7986 with single > > mode. > > > > Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> > > Acked-by: Rob Herring <robh@kernel.org> > > --- > > Documentation/devicetree/bindings/spi/mediatek,spi-mt65xx.yaml | > > 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/Documentation/devicetree/bindings/spi/mediatek,spi- > > mt65xx.yaml b/Documentation/devicetree/bindings/spi/mediatek,spi- > > mt65xx.yaml > > index bfa44acb1bdd..48024b98408a 100644 > > --- a/Documentation/devicetree/bindings/spi/mediatek,spi- > > mt65xx.yaml > > +++ b/Documentation/devicetree/bindings/spi/mediatek,spi- > > mt65xx.yaml > > @@ -41,6 +41,7 @@ properties: > > - mediatek,mt8135-spi > > - mediatek,mt8173-spi > > - mediatek,mt8183-spi > > + - mediatek,mt7986-spi-single > > > > reg: > > maxItems: 1 > > I think that the best way to do this is to better organize the > compatibles > per-hardware, here... or the compatibles list will eventually grow > out of > control for little reason. > > Since "IPM" is a new SPI controller IP, I would expect more and more > MediaTek > SoCs using it in the future, so here's my proposal: Yes, we plan to use this IP with new ICs. > > - Add a generic (const) compatible "mediatek,spi-ipm" to describe the > hardware > - Add an enumeration with "mediatek,mt7986-spi-ipm" as the only > member, as to > prepare this binding for the future. > - Single and quad mode can be expressed with generic SPI bindings! > > Specifically, you can express that with "spi-rx-bus-width" for > SPI_RX_{....} > and "spi-tx-bus-width" for SPI_TX_{....}, so you don't need different > compatibles > for "mediatek,mt7986-spi-single" and "mediatek,mt7896-spi-quad". > > Fast example: > > spi@12345678 { > compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; > reg = <....> > /* Quad mode */ > spi-rx-bus-width = <4>; > spi-tx-bus-width = <4>; > > .... etc .... > } > OK, thanks for your advice. > Regards, > Angelo > >